公开(公告)号：US20090059471A1

公开(公告)日：2009-03-05

申请号：US11909713

申请日：2006-03-17

申请人： Daisuke Fukuda ,  Kiyoshi Matsubara ,  Masahiro Nishigaki

发明人： Daisuke Fukuda ,  Kiyoshi Matsubara ,  Masahiro Nishigaki

IPC分类号： H01G4/12 ,  C04B35/64

CPC分类号： H01G4/1281 ,  C04B35/4682 ,  C04B35/62685 ,  C04B35/62805 ,  C04B35/6281 ,  C04B35/62815 ,  C04B2235/3206 ,  C04B2235/3208 ,  C04B2235/3215 ,  C04B2235/3224 ,  C04B2235/3225 ,  C04B2235/3236 ,  C04B2235/3262 ,  C04B2235/3418 ,  C04B2235/3436 ,  C04B2235/36 ,  C04B2235/5409 ,  C04B2235/5445 ,  C04B2235/6025 ,  C04B2235/652 ,  C04B2235/656 ,  C04B2235/6562 ,  C04B2235/6565 ,  C04B2235/663 ,  C04B2235/72 ,  C04B2235/762 ,  C04B2235/765 ,  C04B2235/784 ,  C04B2235/785 ,  C04B2235/79 ,  C04B2235/80 ,  C04B2235/85 ,  H01G4/1227 ,  H01G4/30 ,  Y10T29/435

摘要： The invention provides a multilayer ceramic capacitor comprising a capacitor body composed by alternately layering dielectric layers and inner electrode layers, and each of the above mentioned dielectric layers contains a plurality of crystal particles, and grain boundary phases comprising interfacial grain boundaries and triple point grain boundaries formed among a plurality of the crystal particles adjacent to one another, and Si—Ba—O compound being formed in 5% or more of the triple point grain boundaries in the entire triple point grain boundaries per unit surface area of the dielectric layer. Accordingly, the multilayer ceramic capacitor has high relative permittivity and is high the temperature property and highly accelerated life test property.

摘要翻译： 本发明提供一种多层陶瓷电容器，其包括通过交替层叠电介质层和内部电极层而构成的电容器体，并且上述每个电介质层包含多个晶体颗粒，并且包含界面晶界和三点晶界的晶界相 形成在彼此相邻的多个晶体颗粒中，并且Si-Ba-O化合物形成在电介质层的每单位表面积的整个三重点晶界的三重点晶界的5％以上。 因此，多层陶瓷电容器具有高的相对介电常数，并且具有高的温度特性和高加速的寿命测试特性。

公开(公告)号：US07057876B2

公开(公告)日：2006-06-06

申请号：US11193284

申请日：2005-07-28

申请人： Yoshihiro Fujioka ,  Kiyoshi Matsubara

发明人： Yoshihiro Fujioka ,  Kiyoshi Matsubara

IPC分类号： H01G4/06 ,  C04B35/46

CPC分类号： B32B18/00 ,  B32B2311/12 ,  B32B2311/22 ,  C01G23/003 ,  C01G23/006 ,  C01P2004/61 ,  C01P2006/40 ,  C04B35/62675 ,  C04B35/6281 ,  C04B35/64 ,  C04B2235/3206 ,  C04B2235/3208 ,  C04B2235/3213 ,  C04B2235/3225 ,  C04B2235/3262 ,  C04B2235/36 ,  C04B2235/5409 ,  C04B2235/5445 ,  C04B2235/6025 ,  C04B2235/652 ,  C04B2235/6584 ,  C04B2235/663 ,  C04B2235/85 ,  C04B2237/346 ,  C04B2237/40 ,  C04B2237/405 ,  C04B2237/407 ,  C04B2237/704 ,  C04B2237/706 ,  H01G4/1227

摘要： A multilayer ceramic capacitor comprises a dielectric layer and an internal electrode layer that are alternately laminated. Barium titanate particles containing an alkaline earth metal component except for Ba in a proportion of not more than 0.2 atomic % (BMTL), and barium titanate particles containing an alkaline earth metal component except for Ba in a proportion of not less than 0.4 atomic % (BMTH) coexist in the dielectric layer in an area ratio of BMTL to BMTH of 0.1 to 9. This provides excellent reliability of capacity temperature characteristic and high-temperature load lifetime, if the dielectric layer is thinned.

摘要翻译： 多层陶瓷电容器包括交替层叠的电介质层和内部电极层。 含有不超过0.2原子％（BMTL）以外的Ba的碱土类金属成分的钛酸钡粒子，除了Ba以外的碱土金属成分的钛酸钡粒子的比例为0.4原子％以上 BMTH）在BMTL与BMTH的面积比为0.1〜9的情况下在电介质层中共存。如果电介质层变薄，则提供容量温度特性和高温负载寿命的极好的可靠性。

公开(公告)号：US20060114641A1

公开(公告)日：2006-06-01

申请号：US11285462

申请日：2005-11-22

申请人： Kenichi Iwasaki ,  Daisuke Fukuda ,  Masahiro Nishigaki ,  Kiyoshi Matsubara ,  Kousei Kamigaki

发明人： Kenichi Iwasaki ,  Daisuke Fukuda ,  Masahiro Nishigaki ,  Kiyoshi Matsubara ,  Kousei Kamigaki

IPC分类号： H01G4/06 ,  C04B35/48

CPC分类号： C04B35/4682 ,  B32B2311/22 ,  C04B35/49 ,  C04B35/62665 ,  C04B35/62805 ,  C04B35/6281 ,  C04B35/62815 ,  C04B35/6303 ,  C04B35/64 ,  C04B2235/3206 ,  C04B2235/3208 ,  C04B2235/3213 ,  C04B2235/3215 ,  C04B2235/3224 ,  C04B2235/3225 ,  C04B2235/3244 ,  C04B2235/3262 ,  C04B2235/36 ,  C04B2235/5445 ,  C04B2235/6025 ,  C04B2235/656 ,  C04B2235/6582 ,  C04B2235/6584 ,  C04B2235/663 ,  C04B2235/72 ,  C04B2235/782 ,  C04B2235/785 ,  C04B2235/79 ,  C04B2235/85 ,  C04B2237/346 ,  C04B2237/405 ,  H01G4/1218 ,  H01G4/1227

摘要： Provided is a multilayer ceramic capacitor having a capacitor body formed by alternately laminating a dielectric layer and an internal electrode layer, and an external electrode formed on both ends of the capacitor body. The dielectric layer has at least two type of barium titanate crystal grains that differ from one another in at least one selected from Ca composition concentration, Sr composition concentration, and Zr composition concentration, and a grain boundary phase. If this multilayer ceramic capacitor employs, as a dielectric layer, a dielectric ceramic that contains barium titanate crystal grains in which part of Ba is substituted by Ca, Sr, or Zr, it is capable of suppressing the grain growth of crystal grains, and improving relative dielectric constant, temperature characteristic, and high-temperature load test characteristic, for example, in high-volume manufacturing using a tunnel type large kiln.

摘要翻译： 提供一种具有通过交替层叠电介质层和内部电极层而形成的电容器主体的多层陶瓷电容器，以及形成在电容器本体的两端的外部电极。 介电层具有至少两种选自Ca组成浓度，Sr组成浓度，Zr组分浓度和晶界相中至少一种彼此不同的钛酸钡晶粒。 如果该多层陶瓷电容器使用含有Ba的一部分被Ca，Sr或Zr取代的钛酸钡晶体的电介质陶瓷，则能够抑制晶粒的晶粒生长，并且提高 相对介电常数，温度特性和高温负荷试验特性，例如在使用隧道式大窑的大批量制造中。

公开(公告)号：US06748507B2

公开(公告)日：2004-06-08

申请号：US10172290

申请日：2002-06-13

申请人： Shumpei Kawasaki ,  Yasushi Akao ,  Kouki Noguchi ,  Atsushi Hasegawa ,  Hiroshi Ohsuga ,  Keiichi Kurakazu ,  Kiyoshi Matsubara ,  Akio Hayakawa ,  Yoshitaka Ito

发明人： Shumpei Kawasaki ,  Yasushi Akao ,  Kouki Noguchi ,  Atsushi Hasegawa ,  Hiroshi Ohsuga ,  Keiichi Kurakazu ,  Kiyoshi Matsubara ,  Akio Hayakawa ,  Yoshitaka Ito

IPC分类号： G06F1200

CPC分类号： G06F9/3001 ,  G06F12/0893 ,  G06F13/36 ,  G06F13/405 ,  G06F15/7817 ,  H04W28/08 ,  H04W52/0216 ,  H04W88/02 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D70/142 ,  Y02D70/26

摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

摘要翻译： 一种单片微计算机，包括：具有中央处理单元和与其连接的高速缓冲存储器的第一总线; 具有动态存储器访问控制电路和与其连接的外部总线接口的第二总线; 用于选择性地连接第一总线和第二总线的断开控制器; 第三总线，其具有与其连接的周边模块，并且具有比第一和第二总线的总线周期更低的总线周期; 以及用于进行数据传送和第二总线与第三总线之间的同步的总线状态控制器。 单片机具有三条分开的内部总线，以减少信号传输路径上的负载能力，从而可以高速实现信号传输。 此外，隔离所需要的没有操作速度的外围模块，从而可以降低功耗。

公开(公告)号：US06493271B2

公开(公告)日：2002-12-10

申请号：US09987957

申请日：2001-11-16

申请人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

发明人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

IPC分类号： G11C1604

CPC分类号： H01L27/11526 ,  G06F9/445 ,  G06F15/7814 ,  G06F15/7821 ,  G11C7/1045 ,  G11C16/0416 ,  G11C16/102 ,  G11C16/105 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11546 ,  Y02D10/43

摘要： A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

摘要翻译： 具有电可擦除和可编程非易失性存储器的半导体器件，例如，包括以行和列布置的存储器单元的可重写非易失性存储器，并且被设置为便于闪存擦除以及多个存储器单元的各个单元的选择性擦除。 用作微计算机芯片的半导体器件还具有处理单元，并且包括：输入端子，用于在处理单元的控制下在闪速存储器被重写的第一操作模式和第二操作模式之间接收用于切换微型计算机的操作模式信号 操作模式，其中在外部连接到微型计算机的分离的写入电路的控制下闪存被重写。

公开(公告)号：US6026020A

公开(公告)日：2000-02-15

申请号：US788198

申请日：1997-01-24

申请人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

发明人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

IPC分类号： G06F9/445 ,  G06F15/78 ,  G11C7/10 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115

CPC分类号： H01L27/11526 ,  G06F15/7814 ,  G06F15/7821 ,  G06F9/445 ,  G11C16/0416 ,  G11C16/102 ,  G11C16/105 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  G11C7/1045 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11546 ,  H01L27/105 ,  Y02B60/185

摘要： A single chip semiconductor integrated circuit device having a central processing unit (CPU) and a flash memory which stores data to be processed by the CPU and which provides data to the CPU through the data bus in response to accessing instructions from the CPU through the address bus. The flash memory is constituted by a plurality of memory blocks each of which has a plurality of electrically programmable nonvolatile memory cells arranged in rows and columns in which each nonvolatile memory cell is coupled to one of a plurality of word lines and one of a plurality of data lines of the flash memory. The memory blocks formed can be facilitated with different memory capacities, including through controlling the number of rows or columns of memory cells associated therewith. Sources of all of the memory cells within each memory block are connected to a single source line which is fed by a predetermined voltage from a corresponding one of plural source voltage control circuits, for flash erasing the memory cells in that memory block in an erasing operation. In accordance with another feature of the flash memory, a control register, included within a device and under the control of the CPU, is employed to control the erasing of data stored in one or more of the memory blocks, simultaneously.

摘要翻译： 具有中央处理单元（CPU）和闪速存储器的单芯片半导体集成电路器件，其存储要由CPU处理的数据，并且响应于通过地址访问来自CPU的指令，通过数据总线向CPU提供数据 总线。 闪存由多个存储块构成，每个存储块具有排列成行和列的多个电可编程非易失性存储单元，其中每个非易失性存储单元耦合到多个字线中的一个，多个字线中的一个 数据线的闪存。 所形成的存储器块可以通过不同的存储器容量来实现，包括通过控制与其相关联的存储器单元的行数或列数来实现。 每个存储块内的所有存储单元的源极连接到单个源极线，该源极线由多个源极电压控制电路中相应的一个源极电压控制电路的预定电压馈送，用于在擦除操作中闪存该存储器块中的存储器单元 。 根据闪速存储器的另一特征，使用包括在设备内并在CPU的控制下的控制寄存器来同时控制存储在一个或多个存储器块中的数据的擦除。

公开(公告)号：US6006304A

公开(公告)日：1999-12-21

申请号：US603211

申请日：1996-02-20

申请人： Hirofumi Mukai ,  Kiyoshi Matsubara

发明人： Hirofumi Mukai ,  Kiyoshi Matsubara

IPC分类号： G06F15/78 ,  G11C16/10 ,  G11C16/32 ,  G06F9/44

CPC分类号： G11C16/32 ,  G06F15/7814 ,  G11C16/102

摘要： A system includes a microcomputer. The microcomputer includes a clock signal circuit, a measuring circuit, a central processing unit, and a flash memory. A user sets a frequency of a clock signal provided by the clock signal circuit. The measuring unit counts a number of cycles of the clock signal in a period specified by reference data. The central processing unit receives the clock signal from the clock signal circuit and operates in accordance with the clock signal. The flash memory stores data which is electrically erased during an erase operation. The erase operation is executed during an erase time which includes a number of cycles of the clock signal calculated by the central processing unit. The central processing unit calculates a time for one cycle of the clock signal as a function of the period specified by the reference data and the number of cycles counted by the measuring unit. The central processing unit then calculates the number of cycles of the clock signal to be allocated as the erase time as a function of the time for one cycle of the clock signal.

摘要翻译： 系统包括微型计算机。 微型计算机包括时钟信号电路，测量电路，中央处理单元和闪存。 用户设置由时钟信号电路提供的时钟信号的频率。 测量单元在由参考数据指定的时间段内对时钟信号的周期数进行计数。 中央处理单元从时钟信号电路接收时钟信号，并根据时钟信号进行操作。 闪存存储在擦除操作期间被电擦除的数据。 在擦除时间期间执行擦除操作，该擦除时间包括由中央处理单元计算出的时钟信号的周期数。 中央处理单元根据由参考数据指定的周期和由测量单元计数的周期数来计算时钟信号的一个周期的时间。 然后，中央处理单元计算作为时钟信号的一个周期的时间的函数的要分配的时钟信号的周期数作为擦除时间。

公开(公告)号：US5991221A

公开(公告)日：1999-11-23

申请号：US16300

申请日：1998-01-30

申请人： Eiichi Ishikawa ,  Yasuyuki Saito ,  Masanao Sato ,  Naoki Yada ,  Kiyoshi Matsubara

发明人： Eiichi Ishikawa ,  Yasuyuki Saito ,  Masanao Sato ,  Naoki Yada ,  Kiyoshi Matsubara

IPC分类号： G11C5/14 ,  G11C16/30 ,  G11C7/00

CPC分类号： G11C16/30 ,  G11C5/14 ,  G11C5/145

摘要： A microcomputer incorporating a flash memory which is erased and programmed electrically in a stable manner within a relatively wide range of external power supply voltages including those for low-voltage operations. The microcomputer comprises a voltage clamp unit including a reference voltage generating circuit and a constant voltage generating circuit. In operation, the voltage clamp unit generates a voltage of a low dependency on a supply voltage and clamps the generated voltage to a voltage level which, within a tolerable range, is lower than a single supply voltage externally furnished. This prevents voltages boosted by boosting circuits operating on the clamped voltage, i.e., programming and erasure voltages, from being dependent on the externally supplied voltage.

公开(公告)号：US5768194A

公开(公告)日：1998-06-16

申请号：US473114

申请日：1995-06-07

申请人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

发明人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

IPC分类号： G06F9/445 ,  G06F15/78 ,  G11C7/10 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  G11C11/34

CPC分类号： H01L27/11526 ,  G06F15/7814 ,  G06F15/7821 ,  G06F9/445 ,  G11C16/0416 ,  G11C16/102 ,  G11C16/105 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  G11C7/1045 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11546 ,  H01L27/105 ,  Y02B60/185

摘要： A single chip semiconductor integrated circuit device having a central processing unit (CPU) and a flash memory which stores data to be processed by the CPU and which provides data to the CPU through the data bus in response to accessing instructions from the CPU through the address bus. The flash memory is constituted by a plurality of memory arrays in which a plurality of word lines are commonly employed for all of the memory arrays and a plurality of data lines are distributed amongst the memory arrays. The nonvolatile memory cells are arranged in a manner in which plural memory blocks are formed. The memory blocks formed can be facilitated with different memory capacities. This is achieved by having one or more rows of memory cells associated with one or more word lines provided within a memory block. Sources of all of the memory cells within each memory block are connected to a single source line which is fed by a predetermined voltage for effecting simultaneous erasure of the memory cells therein from a corresponding one of plural source voltage control circuits. In accordance with another feature of the flash memory, individual ones of plural bit data are assigned to respective ones of the plural memory arrays.

摘要翻译： 具有中央处理单元（CPU）和闪速存储器的单芯片半导体集成电路器件，其存储要由CPU处理的数据，并且响应于通过地址访问来自CPU的指令，通过数据总线向CPU提供数据 总线。 闪存由多个存储器阵列构成，其中多个字线通常用于所有存储器阵列，并且多个数据线分布在存储器阵列之间。 以形成多个存储块的方式配置非易失性存储单元。 形成的存储块可以利用不同的存储容量来促进。 这通过使一行或多行存储器单元与提供在存储器块中的一个或多个字线相关联来实现。 每个存储器块内的所有存储单元的源连接到由预定电压馈送的单个源极线，用于从多个源极电压控制电路中相应的一个同时擦除存储器单元。 根据闪存的另一特征，将多个位数据中的各个数据分配给多个存储器阵列中的相应的数据。

公开(公告)号：US5748977A

公开(公告)日：1998-05-05

申请号：US628241

申请日：1996-04-04

申请人： Shumpei Kawasaki ,  Kaoru Fukada ,  Mitsuru Watabe ,  Kouki Noguchi ,  Kiyoshi Matsubara ,  Isamu Mochizuki ,  Kazufumi Suzukawa ,  Shigeki Masumura ,  Yasushi Akao ,  Eiji Sakakibara

发明人： Shumpei Kawasaki ,  Kaoru Fukada ,  Mitsuru Watabe ,  Kouki Noguchi ,  Kiyoshi Matsubara ,  Isamu Mochizuki ,  Kazufumi Suzukawa ,  Shigeki Masumura ,  Yasushi Akao ,  Eiji Sakakibara

IPC分类号： G06F12/00 ,  G06F12/06 ,  G06F13/42 ,  G06F15/78 ,  G06F13/00

CPC分类号： G06F15/7832 ,  G06F13/4239 ,  G06F15/786

摘要： A microcomputer that is easy to use and connected direct to such memories as dynamic and static RAM's and to other peripheral circuits. The microcomputer has strobe signal output terminals CASH*, CASL* and RAS* for direct connection to a dynamic RAM, and chip select signal output terminals CS0* through CS6* for outputting a chip select signal in parallel with the output from the strobe signal output terminals. The microcomputer further includes address output terminals for outputting a non-multiplexed or multiplexed address signal as needed, and data I/O terminals for selectively outputting the address signal to comply with a multiple-bus interface scheme.