发明授权
- 专利标题: Method of manufacturing a stacked capacitor in a dram
- 专利标题(中): 制造堆叠电容器的方法
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申请号: US457193申请日: 1995-06-01
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公开(公告)号: US5597755A公开(公告)日: 1997-01-28
- 发明人: Natsuo Ajika , Hideaki Arima , Atsushi Hachisuka
- 申请人: Natsuo Ajika , Hideaki Arima , Atsushi Hachisuka
- 申请人地址: JPX Tokyo
- 专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX2-16960 19900126; JPX2-89869 19900403; JPX2-251306 19900919
- 主分类号: H01L27/04
- IPC分类号: H01L27/04 ; H01L21/822 ; H01L21/8242 ; H01L27/10 ; H01L27/108 ; H01L21/70 ; H01L27/00
摘要:
A method of manufacturing a semiconductor memory device having stacked capacitors is disclosed. After forming a capacitor isolating layer on an insulation layer and forming a contact hole in the insulation layer, a first conductive layer is formed on the insulating layer and the capacitor isolating layer and on an inner surface of the contact hole. The first conductive layer is partially etched and removed by using an etch-back technique to be isolated into a first capacitor portion and a second capacitor portion. A dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the dielectric layer.
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