发明授权
- 专利标题: Method of manufacturing semiconductor devices
- 专利标题(中): 制造半导体器件的方法
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申请号: US571732申请日: 1995-12-13
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公开(公告)号: US5599424A公开(公告)日: 1997-02-04
- 发明人: Shoji Matsumoto , Yoshihisa Nagano , Yasuhiro Shimada , Yasufumi Izutsu
- 申请人: Shoji Matsumoto , Yoshihisa Nagano , Yasuhiro Shimada , Yasufumi Izutsu
- 申请人地址: JPX Osaka
- 专利权人: Matsushita Electronics Corporation
- 当前专利权人: Matsushita Electronics Corporation
- 当前专利权人地址: JPX Osaka
- 优先权: JPX6-60883 19940330; JPX6-86686 19940425; JPX6-327667 19941228
- 主分类号: H01L21/302
- IPC分类号: H01L21/302 ; H01L21/02 ; H01L21/3065 ; H01L21/822 ; H01L21/8242 ; H01L21/8246 ; H01L27/04 ; H01L27/10 ; H01L27/105 ; H01L27/108 ; H01L21/00
摘要:
On a silicon substrate, a silicon oxide layer, a first platinum layer, a dielectric film and a second platinum layer are formed, and then the second platinum layer and the dielectric film are dry etched, via a resist layer, in a 1-5 Pa low pressure region with a mixed gas of HBr and 0.sub.2 as the etching gas. As soon as the first platinum layer is exposed, the unetched portion of dielectric film is etched off in a 5-50 Pa high pressure region, and then the first platinum layer is dry etched again in the low pressure region to form a capacitor consisting of a top electrode, a capacitance insulation layer and a bottom electrode in a semiconductor integrated circuit chip. Using this manufacturing method prevents the deterioration in definition caused by the use of a thick resist and the operation failure of circuit elements such as transistors due to over etching on the insulation layer.
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