发明授权
- 专利标题: Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge
- 专利标题(中): 仲裁信令机制,以防止死锁保证访问延迟,并保证扩展桥的采集延迟
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申请号: US366964申请日: 1994-12-30
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公开(公告)号: US5625779A公开(公告)日: 1997-04-29
- 发明人: Gary A. Solomon , Peter D. MacWilliams , George R. Hayek , Nicholas D. Wade , Abid Asghar
- 申请人: Gary A. Solomon , Peter D. MacWilliams , George R. Hayek , Nicholas D. Wade , Abid Asghar
- 申请人地址: CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: CA Santa Clara
- 主分类号: G06F13/364
- IPC分类号: G06F13/364 ; G06F13/40 ; G06F13/36
摘要:
An arbitration signaling mechanism for an intermediate bus coupled between an expansion bridge and a host bridge that manages communication over the intermediate bus. The host bridge includes a CPU posting buffer for posting transactions between a CPU and the expansion bridge, and a DRAM buffer for storing data to be written into the DRAM. The host bridge also includes an arbiter coupled to receive a request signal from the expansion bridge and any other bus agents coupled to the expansion bridge. Responsive to a request from the expansion bridge, the arbiter empties the CPU posting buffer and the DRAM buffer before asserting an acknowledge signal. A passive release method is provided, which includes signaling a passive release semantic by the expansion bridge during a communication cycle in which the expansion bridge has bus control. The host bridge can grant temporary use of the bus to another bus agent before again granting access to the expansion bridge.
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