公开(公告)号：US4785423A

公开(公告)日：1988-11-15

申请号：US5927

申请日：1987-01-22

申请人： Joseph A. Skupnjak ,  Abid Asghar ,  Kirby S. Hallenbeck

发明人： Joseph A. Skupnjak ,  Abid Asghar ,  Kirby S. Hallenbeck

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/24 ,  H03K19/177 ,  G11C7/00 ,  G11C11/34

CPC分类号： G11C16/24

摘要： An improved architecture for an EPROM PAL utilizing two bit lines is disclosed. The drains of the EPROM cells of a given column of an array are coupled together to a first bit line. The first line is coupled to a sensing circuit. The sources of the EPROM cells are coupled together to a second bit line which is then coupled through a current limiting transistor. The gate of the transistor is coupled to the first bit line to receive a feedback signal for controlling the current on the bit lines. The current limiting feature provides for shorter transition periods between "on" and "off" states which results in an improved speed performance of the device.

摘要翻译： 公开了一种利用两位线的EPROM PAL的改进架构。 阵列的给定列的EPROM单元的漏极耦合到第一位线。 第一行耦合到感测电路。 EPROM单元的源极耦合到第二位线，然后通过限流晶体管耦合。 晶体管的栅极耦合到第一位线以接收用于控制位线上的电流的反馈信号。 电流限制功能提供“开”和“关”状态之间较短的过渡周期，这导致器件的速度性能得到改善。

公开(公告)号：US5625779A

公开(公告)日：1997-04-29

申请号：US366964

申请日：1994-12-30

申请人： Gary A. Solomon ,  Peter D. MacWilliams ,  George R. Hayek ,  Nicholas D. Wade ,  Abid Asghar

发明人： Gary A. Solomon ,  Peter D. MacWilliams ,  George R. Hayek ,  Nicholas D. Wade ,  Abid Asghar

IPC分类号： G06F13/364 ,  G06F13/40 ,  G06F13/36

CPC分类号： G06F13/364 ,  G06F13/4031 ,  G06F13/4036

摘要： An arbitration signaling mechanism for an intermediate bus coupled between an expansion bridge and a host bridge that manages communication over the intermediate bus. The host bridge includes a CPU posting buffer for posting transactions between a CPU and the expansion bridge, and a DRAM buffer for storing data to be written into the DRAM. The host bridge also includes an arbiter coupled to receive a request signal from the expansion bridge and any other bus agents coupled to the expansion bridge. Responsive to a request from the expansion bridge, the arbiter empties the CPU posting buffer and the DRAM buffer before asserting an acknowledge signal. A passive release method is provided, which includes signaling a passive release semantic by the expansion bridge during a communication cycle in which the expansion bridge has bus control. The host bridge can grant temporary use of the bus to another bus agent before again granting access to the expansion bridge.

摘要翻译： 耦合在扩展桥和主桥之间的中间总线的仲裁信令机制，用于管理通过中间总线的通信。 主桥包括用于在CPU和扩展桥之间发布事务的CPU发布缓冲器，以及用于存储要写入到DRAM中的数据的DRAM缓冲器。 主桥还包括耦合以从扩展桥接器和耦合到扩展桥的任何其它总线代理接收请求信号的仲裁器。 响应于扩展桥的请求，仲裁器在确认确认信号之前清空CPU发布缓冲区和DRAM缓冲区。 提供了一种被动释放方法，其包括在扩展桥具有总线控制的通信周期期间通过扩展桥信令发送被动释放语义。 主桥可以在再次允许进入扩建桥之前，暂时使用公交车给另一个总线代理。

公开(公告)号：US4878200A

公开(公告)日：1989-10-31

申请号：US139450

申请日：1987-12-30

申请人： Abid Asghar ,  James R. Donnell

发明人： Abid Asghar ,  James R. Donnell

IPC分类号： H03K19/177

CPC分类号： H03K19/17712

摘要： An erasable programmable logic device which includes a programmable AND memory array and a macrocell processing the output of the AND array allows product term sharing/allocation by adjacent macrocells. Two groups of four product terms each are coupled to each macrocell, wherein the OR'ing of each group of four product terms is each coupled to a multiplexor. One group is also coupled to a previously adjacent macrocell and the second group is coupled to a subsequently adjacent macrocell. A third and fourth multiplexor accept four product terms from each of the adjacent macrocells and the output of the four multiplexors are coupled to an OR gate. When a multiplexor is activated, it couples each grouping of four product terms to the OR gate and the output of the OR gate is coupled to an I/O circuit which emulates combinatory and sequential logic circuits. By selecting appropriate multiplexors each eight product term macrocell is capable of processing 0, 4, 8, 12 or 16 product terms. An alternative embodiment has three groupings of product terms wherein only two of the groupings are shared by adjacent macrocells.

摘要翻译： 包括可编程AND存储器阵列的可擦除可编程逻辑器件和处理AND阵列的输出的宏单元允许由相邻宏单元进行产品项共享/分配。 两组四个乘积项分别耦合到每个宏单元，其中每组四个乘积项的OR'分别耦合到多路复用器。 一组也耦合到先前相邻的宏小区，而第二组耦合到随后相邻的宏小区。 第三和第四多路复用器接收来自每个相邻宏单元的四个乘积项，并且四个多路复用器的输出耦合到或门。 当复用器被激活时，它将四个乘积项的每组分组耦合到或门，并且OR门的输出耦合到模拟组合和顺序逻辑电路的I / O电路。 通过选择合适的多路复用器，每个八个产品项宏单元能够处理0,4,8,12或16个产品项。 替代实施例具有三组产品术语，其中只有两个分组由相邻宏小区共享。