发明授权
US5652168A Method of forming a semiconductor device having a capacitor with
improved element isolation and operation rate
失效
一种具有电容器的半导体器件的形成方法，所述电容器具有改进的元件隔离和操作速率
- 专利标题： Method of forming a semiconductor device having a capacitor with improved element isolation and operation rate
- 专利标题（中）： 一种具有电容器的半导体器件的形成方法，所述电容器具有改进的元件隔离和操作速率
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申请号： US385517申请日： 1995-02-08
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公开(公告)号： US5652168A公开(公告)日： 1997-07-29
- 发明人: Shigeki Komori , Katsuhiro Tsukamoto
- 申请人： Shigeki Komori , Katsuhiro Tsukamoto
- 申请人地址： JPX Tokyo
- 专利权人： Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人： Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX4-053835 19920312; JPX5-008475 19930121
- 主分类号： H01L27/04
- IPC分类号： H01L27/04 ; H01L21/02 ; H01L21/285 ; H01L21/822 ; H01L21/8242 ; H01L27/10 ; H01L27/108 ; H01L29/41 ; H01L21/70 ; H01L27/00
摘要：
A lower electrode of a capacitor for use in a semiconductor device includes a first semiconductor layer having a predetermined impurity concentration and a second semiconductor layer having an impurity concentration higher than that of the first semiconductor layer. As a result, intensification of an electric field at an end portion of the capacitor can be reduced. In addition, a word line is formed of a buffer layer and a main conductor layer to reduce a parasitic capacitance between the lower electrode of the capacitor and the word line.
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