Peripheral structure of a chip as a semiconductor device, and manufacturing method thereof
    1.
    发明授权
    Peripheral structure of a chip as a semiconductor device, and manufacturing method thereof 有权
    作为半导体器件的芯片的外围结构及其制造方法

    公开(公告)号:US06211070B1

    公开(公告)日:2001-04-03

    申请号:US09329494

    申请日:1999-06-10

    IPC分类号: H01L214763

    CPC分类号: H01L21/78 H01L21/743

    摘要: On a surface of a semiconductor substrate within a device forming region, a MOS transistor including a gate electrode, gate oxide film and source•drain is formed. An insulating layer is formed on the surface of the semiconductor substrate. In an opening of the insulating layer above the source•drain, a tungsten plug is formed. At a dicing line portion, the insulating layer has a trench portion. The trench portion is formed to surround the device forming region. A tungsten street having a top surface continuous to the top surface of the insulating layer is formed in the trench. By this semiconductor device, short-circuit between bonding pads and the like can be prevented, and the reliability can be improved.

    摘要翻译: 在器件形成区域内的半导体衬底的表面上形成包括栅电极,栅极氧化膜和源极的MOS晶体管。 绝缘层形成在半导体衬底的表面上。 在源极上方的绝缘层的开口中,形成钨插塞。 在切割线部分,绝缘层具有沟槽部分。 沟槽部形成为围绕器件形成区域。 在沟槽中形成具有与绝缘层的顶表面连续的顶表面的钨街。 通过该半导体装置,能够防止接合焊盘之间的短路等,能够提高可靠性。

    PN junction trench isolation type semiconductor device
    3.
    发明授权
    PN junction trench isolation type semiconductor device 失效
    PN结沟隔离型半导体器件

    公开(公告)号:US5525821A

    公开(公告)日:1996-06-11

    申请号:US383672

    申请日:1995-02-01

    摘要: There is disclosed a semiconductor device including a plurality of P well regions (4) and a P well region (41) insulated from each other by a plurality of trench isolating layers (10) formed regularly in predetermined spaced relation with each other and having the same depth. The outermost P well region (41) isolatedly formed externally of an outermost trench isolating layer (10A) is made as deep as the trench isolating layers (10) and, accordingly, is made deeper than the P well regions (4) except the outermost P well region (41). This provides for the alleviation of the electric field concentration generated in the bottom edge of the outermost isolating layer of trench structure, thereby achieving the semiconductor device having an improved device breakdown voltage and a method of fabricating the same.

    摘要翻译: 公开了一种半导体器件,其包括多个P阱区域(P阱区域)和P阱区域(P),P阱区域(41)通过以规定间隔开的关系规则形成的多个沟槽隔离层(10)彼此绝缘,并且具有 相同的深度 隔离地形成在最外层沟槽隔离层(10A)的外部的最外层的P阱区(41)制成与沟槽隔离层(10)一样深,因此比P阱区(4)更深,除了最外层 P井区域(41)。 这提供了减轻在沟槽结构的最外隔离层的底部边缘产生的电场浓度,从而实现了具有改进的器件击穿电压的半导体器件及其制造方法。

    Semiconductor device for element isolation and manufacturing method
thereof
    4.
    发明授权
    Semiconductor device for element isolation and manufacturing method thereof 失效
    元件隔离半导体器件及其制造方法

    公开(公告)号:US5457339A

    公开(公告)日:1995-10-10

    申请号:US252629

    申请日:1994-06-02

    CPC分类号: H01L21/763

    摘要: A semiconductor device for element isolation comprises a semiconductor substrate having an impurity region of a first conductivity type whose impurity concentration attains the maximum at a predetermined depth from the surface in the depth direction, a trench formed to a predetermined depth in the impurity region of the first conductivity type, and an impurity diffusion region of the first conductivity type formed in the trench with an oxide film interposed and having only its bottom portion connected to the impurity region of the first conductivity type of the semiconductor substrate. In the semiconductor device, a uniform P.sup.+ high concentration region is substantially formed in a bottom portion of an isolation region, so that an isolation threshold value is not affected.

    摘要翻译: 用于元件隔离的半导体器件包括半导体衬底,该半导体衬底具有第一导电类型的杂质区域,其杂质浓度在与深度方向的表面相距预定深度处达到最大值,在该杂质区域中形成预定深度的沟槽 第一导电类型和沟槽中形成的第一导电类型的杂质扩散区域,其中氧化膜被插入并且仅其底部部分连接到半导体衬底的第一导电类型的杂质区域。 在半导体装置中,在隔离区域的底部大致形成均匀的P +高浓度区域,从而不影响隔离阈值。

    Method of manufacturing a semiconductor device
    5.
    发明授权
    Method of manufacturing a semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号:US5401671A

    公开(公告)日:1995-03-28

    申请号:US167280

    申请日:1993-12-15

    摘要: A semiconductor device has an upper well of a first conductivity type formed from the surface of an active region separated by an isolation oxide film at the surface of a semiconductor substrate to a predetermined depth. A first conductivity type layer of high concentration is formed along the entire region of an active region to enclose the bottom of the upper well of the first conductivity type. A lower well of the first conductivity type of a predetermined thickness is formed as a buried layer to enclose the bottom of the first conductivity type layer of high concentration. According to this structure, the spreadout of impurities into the active region due to diffusion at the time of thermal treatment is suppressed. The semiconductor device has the wells and the buried layer of high concentration formed by implanting impurities after the step of forming the isolation oxide film, so that diffusion of impurities into the active region due to thermal treatment at the time of isolation oxide film formation is suppressed. As a result, degradation of channel effect is prevented in miniaturization of the semiconductor device.

    摘要翻译: 半导体器件具有由半导体衬底的表面上的隔离氧化膜分隔成预定深度的由有源区的表面形成的第一导电类型的上阱。 沿着有源区域的整个区域形成高浓度的第一导电型层,以包围第一导电类型的上阱的底部。 形成预定厚度的第一导电类型的下阱作为掩埋层以包围高浓度的第一导电类型层的底部。 根据该结构,能够抑制由于热处理时的扩散而使杂质向活性区域的扩散。 半导体器件具有在形成隔离氧化膜的步骤之后通过注入杂质形成的阱和高浓度的掩埋层,从而抑制了隔离氧化膜形成时由于热处理而导致的杂质向有源区的扩散 。 结果,半导体器件的小型化防止沟道效应的劣化。

    Semiconductor field effect device having channel stop and channel region
formed in a well and manufacturing method therefor
    6.
    发明授权
    Semiconductor field effect device having channel stop and channel region formed in a well and manufacturing method therefor 失效
    具有在井中形成的通道停止和通道区域的半导体场效应器件及其制造方法

    公开(公告)号:US5141882A

    公开(公告)日:1992-08-25

    申请号:US816546

    申请日:1991-12-30

    摘要: A method of forming a well on a semiconductor substrate and a transistor on the main surface of this well. A mask exposing a region for the well is formed on the main surface of the semiconductor substrate. Subsequently, ions of impurities for forming the well are implanted on the main surface of the region for the well of the semiconductor substrate using this mask with high energy giving concentration distribution of impurities which becomes maximum at a place deeper than a region for a transistor. Subsequently, ions of impurities of the same conductivity type as that of ions for forming the well are implanted on the main surface of the region for the well of the semiconductor substrate using the mask with low energy giving concentration distribution of impurities in which impurities stay in the region for the channel of the transistor. According to this method, since the formation of the well and channel ion implantation are performed using the same mask, the number of photolithography processes is decreased. In addition, in forming the well, since it is not necessary to diffuse the impurity ions by heat, manufacturing time can be shortened. In addition, since ions of impurities are implanted in the channel region of the transistor, a punch through of the transistor can be prevented.

    摘要翻译: 在该阱的主表面上的半导体衬底和晶体管上形成阱的方法。 在半导体基板的主表面上形成露出用于阱的区域的掩模。 接着,使用该掩膜,在半导体衬底的阱的区域的主表面上注入用于形成阱的离子,从而在比晶体管的区域更深的位置处产生最大的杂质浓度分布。 随后,使用具有低能量的掩模,在半导体衬底的阱的区域的主表面上注入与用于形成阱的离子相同的导电类型的杂质的离子,得到杂质保持在其中的杂质的浓度分布 晶体管通道的区域。 根据该方法,由于使用相同的掩模进行阱和沟道离子注入的形成,所以光刻工序的数量减少。 此外,在形成阱时,由于不需要通过加热来扩散杂质离子,因此可以缩短制造时间。 此外,由于杂质的离子注入在晶体管的沟道区域中,所以可以防止晶体管的穿通。

    Semiconductor memory device having buried structure to suppress soft
errors
    7.
    发明授权
    Semiconductor memory device having buried structure to suppress soft errors 失效
    具有掩埋结构以抑制软错误的半导体存储器件

    公开(公告)号:US5047818A

    公开(公告)日:1991-09-10

    申请号:US662989

    申请日:1991-02-28

    CPC分类号: H01L27/10805

    摘要: A semiconductor memory device comprises a capacitor and a transistor formed on a main surface of a semiconductor substrate and a buried layer of high impurity concentration formed in the substrate, wherein the buried layer has the same conductivity type as that of the substrate and is formed shallow under the capacitor and deep under the transistor.

    摘要翻译: 半导体存储器件包括电容器和形成在半导体衬底的主表面上的晶体管和形成在衬底中的高杂质浓度的掩埋层,其中掩埋层具有与衬底相同的导电类型并形成浅 在电容器下面和深深的晶体管下面。

    Semiconductor memory device and method for making the same
    10.
    发明授权
    Semiconductor memory device and method for making the same 失效
    半导体存储器件及其制造方法

    公开(公告)号:US5883408A

    公开(公告)日:1999-03-16

    申请号:US296988

    申请日:1994-08-26

    CPC分类号: H01L27/10805

    摘要: A semiconductor memory device comprises a capacitor and a transistor formed on a main surface of a semiconductor substrate and a buried layer of high impurity concentration formed in the substrate, wherein the buried layer has the same conductivity type as that of the substrate and is formed shallow under the capacitor and deep under the transistor.

    摘要翻译: 半导体存储器件包括电容器和形成在半导体衬底的主表面上的晶体管和形成在衬底中的高杂质浓度的掩埋层,其中掩埋层具有与衬底相同的导电类型并形成浅 在电容器下面和深深的晶体管下面。