Invention Grant
- Patent Title: Process for fabricating phase shift mask and process of semiconductor integrated circuit device
- Patent Title (中): 制造相移掩模和半导体集成电路器件的工艺
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Application No.: US383839Application Date: 1995-02-06
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Publication No.: US5677092APublication Date: 1997-10-14
- Inventor: Toshitsugu Takekuma , Haruo Ii , Kazuya Ito
- Applicant: Toshitsugu Takekuma , Haruo Ii , Kazuya Ito
- Applicant Address: JPX Tokyo JPX Tokyo
- Assignee: Hitachi, Ltd.,Hitachi VLSI Engineering Corp.
- Current Assignee: Hitachi, Ltd.,Hitachi VLSI Engineering Corp.
- Current Assignee Address: JPX Tokyo JPX Tokyo
- Priority: JPX4-192019 19920720
- Main IPC: G03F1/26
- IPC: G03F1/26 ; G03F1/30 ; G03F1/36 ; G03F1/40 ; G03F1/68 ; G03F1/70 ; G03F1/80 ; G06F17/50 ; H01L21/027 ; G03F7/00
Abstract:
When the data of a mask pattern of a phase shift mask is to be made, the pattern data is separated into a real pattern data layer having the data of real patterns and a phase shift pattern data layer having the data of phase shift patterns. After this, it is verified whether or not the mask pattern satisfies the regulation of the gap of in-phase patterns, in which lights having transmitted through patterns adjacent to each other are in phase. It is also verified whether or not the mask pattern satisfies the regulation of the gap of out-of-phase patterns, in which lights having transmitted through patterns adjacent to each other are out of phase.
Public/Granted literature
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