公开(公告)号：US5217917A

公开(公告)日：1993-06-08

申请号：US496280

申请日：1990-03-20

申请人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takemuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

发明人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takemuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

IPC分类号： G11C5/00 ,  G11C5/02 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/00 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50

CPC分类号： G11C29/027 ,  G11C11/4074 ,  G11C11/4082 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50012 ,  G11C5/00 ,  G11C5/025 ,  G11C7/1045 ,  G11C11/401 ,  G11C2029/5006 ,  G11C29/78

摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

摘要翻译： 提供了一种半导体存储器件，其包括适于形成具有不同封装规格，不同位结构和不同工作模式的大量类型的DRAM的衬底布置。 结合这些，接合垫被布置在适于不同包装类型的最佳位置处。 还提供了各种布局布置以最小化空间并改善访问时间。 提供了额外的功能，包括改进的输出缓冲器电路，保护电路和测试方法以便于半导体存储器件的操作。

公开(公告)号：US5677092A

公开(公告)日：1997-10-14

申请号：US383839

申请日：1995-02-06

申请人： Toshitsugu Takekuma ,  Haruo Ii ,  Kazuya Ito

发明人： Toshitsugu Takekuma ,  Haruo Ii ,  Kazuya Ito

IPC分类号： G03F1/26 ,  G03F1/30 ,  G03F1/36 ,  G03F1/40 ,  G03F1/68 ,  G03F1/70 ,  G03F1/80 ,  G06F17/50 ,  H01L21/027 ,  G03F7/00

CPC分类号： G03F1/30 ,  G03F1/26 ,  Y10S430/143

摘要： When the data of a mask pattern of a phase shift mask is to be made, the pattern data is separated into a real pattern data layer having the data of real patterns and a phase shift pattern data layer having the data of phase shift patterns. After this, it is verified whether or not the mask pattern satisfies the regulation of the gap of in-phase patterns, in which lights having transmitted through patterns adjacent to each other are in phase. It is also verified whether or not the mask pattern satisfies the regulation of the gap of out-of-phase patterns, in which lights having transmitted through patterns adjacent to each other are out of phase.

摘要翻译： 当要进行相移掩模的掩模图案的数据时，将图案数据分离成具有实数图案的实际图案数据层和具有相移图案的数据的相移图案数据层。 此后，验证掩模图案是否满足彼此相邻的透过图案的光同相的同相图案的间隙的调节。 还验证了掩模图案是否满足彼此相邻的具有透射图案的光异相的异相图案的间隙的调节。

公开(公告)号：US5426613A

公开(公告)日：1995-06-20

申请号：US972907

申请日：1992-11-06

申请人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takekuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

发明人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takekuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

IPC分类号： G11C5/00 ,  G11C5/02 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/00 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C29/027 ,  G11C11/4074 ,  G11C11/4082 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50012 ,  G11C5/00 ,  G11C5/025 ,  G11C7/1045 ,  G11C11/401 ,  G11C2029/5006 ,  G11C29/78

摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

摘要翻译： 提供了一种半导体存储器件，其包括适于形成具有不同封装规格，不同位结构和不同工作模式的大量类型的DRAM的衬底布置。 结合这些，接合垫被布置在适于不同包装类型的最佳位置处。 还提供了各种布局布置以最小化空间并改善访问时间。 提供了额外的功能，包括改进的输出缓冲器电路，保护电路和测试方法以便于半导体存储器件的操作。

公开(公告)号：US5805513A

公开(公告)日：1998-09-08

申请号：US432867

申请日：1995-05-02

申请人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takekuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

发明人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takekuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

IPC分类号： G11C5/00 ,  G11C5/02 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/00 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/027 ,  G11C11/4074 ,  G11C11/4082 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50012 ,  G11C5/00 ,  G11C5/025 ,  G11C7/1045 ,  G11C11/401 ,  G11C2029/5006 ,  G11C29/78

摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.