发明授权
- 专利标题: Variable depth and width memory device
- 专利标题(中): 可变深度和宽度的存储设备
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申请号: US555109申请日: 1995-11-08
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公开(公告)号: US5717901A公开(公告)日: 1998-02-10
- 发明人: Chiakang Sung , Wanli Chang , Joseph Huang , Richard G. Cliff
- 申请人: Chiakang Sung , Wanli Chang , Joseph Huang , Richard G. Cliff
- 申请人地址: CA San Jose
- 专利权人: Altera Corporation
- 当前专利权人: Altera Corporation
- 当前专利权人地址: CA San Jose
- 主分类号: H03K19/173
- IPC分类号: H03K19/173 ; H03K19/177 ; G06F12/00
摘要:
A programmable variable depth and width random-access memory circuit is provided. The memory circuit contains rows and columns of memory cells for storing data. A row decoder is used to address individual rows of the memory cells. Column address circuitry receives a column address signal and a width and depth selection signal. A column decoder within the column address circuitry addresses one or more columns of memory cells of the RAM array based on the selected width of the array. The output of the column decoder is routed to the appropriate column or columns of memory cells by a pattern of fixed connections and a group of programmable multiplexers. The number of data output lines to which data signals are provided is determined by the selected width of the RAM array. The output circuitry contains a group of programmable demultiplexers and a routing array having a pattern of fixed connections suitable for passing data signals from the RAM array to the selected number of data output lines.
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