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    Programmable logic array integrated circuits
    2.
    发明授权
    Programmable logic array integrated circuits 失效
    可编程逻辑阵列集成电路

    公开(公告)号：US5828229A

    公开(公告)日：1998-10-27

    申请号：US847004

    申请日：1997-05-01

    申请人： Richard G. Cliff ,  L. Todd Cope ,  Cameron McClintock ,  William Leong ,  James Allen Watson ,  Joseph Huang ,  Bahram Ahanin ,  Chiakang Sung ,  Wanli Chang

    发明人： Richard G. Cliff ,  L. Todd Cope ,  Cameron McClintock ,  William Leong ,  James Allen Watson ,  Joseph Huang ,  Bahram Ahanin ,  Chiakang Sung ,  Wanli Chang

    IPC分类号： G01R31/3185 ,  G11C8/12 ,  G11C8/16 ,  G11C29/32 ,  H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/1737 ,  G11C29/32 ,  G11C8/12 ,  G11C8/16 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1776 ,  H03K19/17764 ,  G01R31/318516

    摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors. A relatively large block of random access memory ("RAM") may be provided on the device for use as read-only memory ("ROM") or RAM during operation of the device to perform logic. The RAM block is connected in the circuitry of the device so that it can be programmed and verified compatibly with other memory on the device. Thereafter the circuitry of the RAM block allows it to be switched over to operation as RAM or ROM during logic operation of the device.

    摘要翻译： 可编程逻辑阵列集成电路具有多个可编程逻辑模块，它们被组合在多个逻辑阵列块（“LAB”）中。 LAB以二维阵列布置在电路上。 提供一个导线网络，用于将任何逻辑模块与任何其他逻辑模块相互连接。 此外，相邻或附近的逻辑模块可以彼此连接，用于在逻辑模块之间提供进位链和/或用于将两个或多个模块连接在一起以提供更复杂的逻辑功能而不必利用一般互连的特殊目的 网络。 提供了所谓的快速或通用导体的另一网络，用于在整个电路中分布广泛使用的逻辑信号，例如时钟和清除信号。 多路复用器可以以各种方式用于减少信号导体之间所需的可编程互连数量。 随机存取存储器（“RAM”）相对较大的块可以在设备的操作期间被提供在设备上用作只读存储器（“ROM”）或RAM，以执行逻辑。 RAM块连接在设备的电路中，使其可以与设备上的其他存储器进行编程和验证。 此后，RAM块的电路允许在设备的逻辑运行期间将其切换到作为RAM或ROM的操作。

    Variable depth and width memory device
    5.
    发明授权
    Variable depth and width memory device 失效
    可变深度和宽度的存储设备

    公开(公告)号：US5717901A

    公开(公告)日：1998-02-10

    申请号：US555109

    申请日：1995-11-08

    申请人： Chiakang Sung ,  Wanli Chang ,  Joseph Huang ,  Richard G. Cliff

    发明人： Chiakang Sung ,  Wanli Chang ,  Joseph Huang ,  Richard G. Cliff

    IPC分类号： H03K19/173 ,  H03K19/177 ,  G06F12/00

    CPC分类号： H03K19/1776 ,  H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17764

    摘要： A programmable variable depth and width random-access memory circuit is provided. The memory circuit contains rows and columns of memory cells for storing data. A row decoder is used to address individual rows of the memory cells. Column address circuitry receives a column address signal and a width and depth selection signal. A column decoder within the column address circuitry addresses one or more columns of memory cells of the RAM array based on the selected width of the array. The output of the column decoder is routed to the appropriate column or columns of memory cells by a pattern of fixed connections and a group of programmable multiplexers. The number of data output lines to which data signals are provided is determined by the selected width of the RAM array. The output circuitry contains a group of programmable demultiplexers and a routing array having a pattern of fixed connections suitable for passing data signals from the RAM array to the selected number of data output lines.

    摘要翻译： 提供了可编程可变深度和宽度随机存取存储器电路。 存储器电路包含用于存储数据的存储单元的行和列。 行解码器用于寻址存储器单元的各行。 列地址电路接收列地址信号和宽度和深度选择信号。 列地址电路中的列解码器基于阵列的选定宽度来寻址RAM阵列的一列或多列存储单元。 列解码器的输出通过固定连接和一组可编程多路复用器的模式路由到存储器单元的适当列或列。 提供数据信号的数据输出线的数量由RAM阵列的选定宽度决定。 输出电路包含一组可编程解复用器和具有适于将数据信号从RAM阵列传递到选定数量的数据输出线的固定连接图案的路由阵列。

    High-speed programmable interconnect
    6.
    发明授权
    High-speed programmable interconnect 有权
    高速可编程互连

    公开(公告)号：US06384629B2

    公开(公告)日：2002-05-07

    申请号：US09738403

    申请日：2000-12-15

    申请人： Joseph Huang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Richard G. Cliff

    发明人： Joseph Huang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Richard G. Cliff

    IPC分类号： H01L2500

    CPC分类号： H03K19/17736 ,  G01R31/318555 ,  G06F11/2273 ,  H03K19/17792

    摘要： An improved interconnection between horizontal conductors and the input to logic elements. A signal regeneration circuit is provided in the path between the horizontal conductor and the logic element, thereby isolating and boosting the signal. This allows for faster switching operation. A path is provided allowing the selective routing of signals from the horizontal conductors to the vertical conductors, without passing through a logic element. Also, a path is provided to allow a horizontal conductors to be routed to any of a plurality of vertical conductors.

    摘要翻译： 水平导体与逻辑元件输入之间的互连改善。 在水平导体和逻辑元件之间的路径中提供信号再生电路，从而隔离和升高信号。 这允许更快的切换操作。 提供路径，允许从水平导体到垂直导体的信号的选择性路由，而不通过逻辑元件。 而且，提供了一种路径，以允许水平导体被路由到多个垂直导体中的任何一个。

    PCI-compatible programmable logic devices
    9.
    发明授权
    PCI-compatible programmable logic devices 有权
    PCI兼容的可编程逻辑器件

    公开(公告)号：US06271681B1

    公开(公告)日：2001-08-07

    申请号：US09395886

    申请日：1999-09-14

    申请人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  David W. Mendel ,  Bruce B. Pedersen ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

    发明人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  David W. Mendel ,  Bruce B. Pedersen ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

    IPC分类号： H03K19177

    CPC分类号： H03K19/1774 ,  H03K19/17744

    摘要： A programmable logic integrated circuit device has several features which help it perform according to the PCI Special Interest Group's Peripheral Component Interface (“PCI”) signaling protocol. Regions of programmable logic within the device are closely coupled to the data signal output pins and clock signal input pins such that delay between application of a clock signal to the device and output of a data signal from the device is within PCI signal standards for delay. The device also includes output circuitry that can be configured to selectively invert signals to output enable and data input enable terminals of the output circuitry.

    摘要翻译： 可编程逻辑集成电路器件具有几个功能，可帮助其根据PCI特殊兴趣组的外设组件接口（“PCI”）信令协议执行。 器件内的可编程逻辑区域紧密耦合到数据信号输出引脚和时钟信号输入引脚，使得施加时钟信号与器件之间的延迟和来自器件的数据信号的输出之间的延迟处于用于延迟的PCI信号标准之内。 该器件还包括可被配置为选择性地将信号反转到输出电路的输出使能和数据输入使能端的输出电路。

    Programmable logic array integrated circuit devices with interleaved logic array blocks
    10.
    发明授权
    Programmable logic array integrated circuit devices with interleaved logic array blocks 有权
    具有交错逻辑阵列块的可编程逻辑阵列集成电路器件

    公开(公告)号：US06204688B1

    公开(公告)日：2001-03-20

    申请号：US09208124

    申请日：1998-12-09

    申请人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  David W. Mendel ,  Bruce B. Pedersen ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

    发明人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  David W. Mendel ,  Bruce B. Pedersen ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

    IPC分类号： H03K19177

    CPC分类号： H03K19/17736 ,  H03K19/04 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17796

    摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Each row has a plurality of adjacent horizontal conductors, and each column has a plurality of adjacent vertical conductors. The regions in a row are interspersed with groups of local conductors which interconnect the adjacent regions and the associated horizontal and vertical conductors. The local conductors can also be used for intra-region communication, as well as communication between adjacent regions. Secondary signals such as clocks and clears for the regions can be drawn either from dedicated secondary signal conductors or normal region inputs. Memory cell requirements for region input signal selection are reduced by various techniques for sharing these memory cells.

    摘要翻译： 可编程逻辑阵列集成电路器件包括以这种区域的交叉行和列的二维阵列布置在器件上的可编程逻辑的多个区域。 每行具有多个相邻的水平导体，并且每列具有多个相邻的垂直导体。 一排中的区域散布有互连相邻区域和相关联的水平和垂直导体的局部导体组。 本地导体也可用于区域内通信，以及相邻区域之间的通信。 辅助信号，例如时钟和区域的清除可以从专用辅助信号导体或正常区域输入中提取。 区域输入信号选择的存储单元要求通过用于共享这些存储单元的各种技术而减少。