发明授权
- 专利标题: DRAM cell arrangement and method for its manufacture
- 专利标题(中): DRAM单元布置及其制造方法
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申请号: US645503申请日: 1996-05-14
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公开(公告)号: US5736761A公开(公告)日: 1998-04-07
- 发明人: Lothar Risch , Franz Hofmann , Wolfgang Roesner , Wolfgang Krautschneider
- 申请人: Lothar Risch , Franz Hofmann , Wolfgang Roesner , Wolfgang Krautschneider
- 申请人地址: DEX
- 专利权人: Siemens Aktiengesellschaft
- 当前专利权人: Siemens Aktiengesellschaft
- 当前专利权人地址: DEX
- 优先权: DEX19519159.5 19950524
- 主分类号: H01L21/8242
- IPC分类号: H01L21/8242 ; H01L27/108 ; H01L29/76 ; H01L29/94 ; H01L31/119
摘要:
The DRAM cell arrangement has one vertical MOS transistor per memory cell, whose first source/drain region adjoins a trenched bitline (5), whose gate electrode (13) is connected with a trenched wordline and whose second source/drain region (3) adjoins a substrate main surface (1). A capacitor dielectric (16), which is in particular a ferroelectric or paraelectric layer, is arranged on at least the second source/drain region and a capacitor plate (17) is arranged on the dielectric, so that the second source/drain region (3) acts additionally as a memory node. The DRAM cell arrangement can be manufactured with a memory cell surface of 4 F.sup.2.