- 专利标题: Semiconductor integrated circuit device having power reduction mechanism
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申请号: US714994申请日: 1996-09-17
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公开(公告)号: US5880604A公开(公告)日: 1999-03-09
- 发明人: Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
- 申请人: Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
- 申请人地址: JPX Tokyo
- 专利权人: Hitachi, Ltd.
- 当前专利权人: Hitachi, Ltd.
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX4-094070 19920414; JPX4-094077 19920414; JPX4-345901 19921225; JPX5-022392 19930210; JPX5-231234 19930917
- 主分类号: H01L27/00
- IPC分类号: H01L27/00 ; H01L27/02 ; H03K3/356 ; H03K19/00 ; H03K19/094 ; H03K19/20 ; H03K19/0948 ; H03K19/096
摘要:
A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.
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