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    Semiconductor integrated circuit device having power reduction mechanism
    4.
    发明授权
    Semiconductor integrated circuit device having power reduction mechanism 失效
    具有功率降低机构的半导体集成电路装置

    公开(公告)号：US06404239B1

    公开(公告)日：2002-06-11

    申请号：US09613594

    申请日：2000-07-10

    申请人： Takayuki Kawahara ,  Ryoichi Hori ,  Masashi Horiguchi ,  Ryoichi Kurihara ,  Kiyoo Itoh ,  Masakazu Aoki ,  Takeshi Sakata ,  Kunio Uchiyama

    发明人： Takayuki Kawahara ,  Ryoichi Hori ,  Masashi Horiguchi ,  Ryoichi Kurihara ,  Kiyoo Itoh ,  Masakazu Aoki ,  Takeshi Sakata ,  Kunio Uchiyama

    IPC分类号： H03K1920

    CPC分类号： H03K3/356113 ,  H01L27/0218 ,  H03K19/0016

    摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

    摘要翻译： 半导体集成电路器件由各自设置有至少两个MOS晶体管的逻辑门组成。 逻辑门连接到第一电势点和第二电位点。 半导体集成电路装置包括连接在逻辑门与第一电位点之间和/或逻辑门与第二电势点之间的电流控制装置，用于根据操作状态控制在逻辑门中流动的电流的值 逻辑门。 该电路可用于在高功耗模式和低功耗模式之间循环运行的器件，例如具有用于功率降低的操作模式和低功率备用或睡眠模式的微处理器。

    Semiconductor integrated circuit device having power reduction mechanism
    8.
    发明申请
    Semiconductor integrated circuit device having power reduction mechanism 失效
    具有降压机构的半导体集成电路装置

    公开(公告)号：US20080072085A1

    公开(公告)日：2008-03-20

    申请号：US11979100

    申请日：2007-10-31

    申请人： Masashi Horiguchi ,  Kunio Uchiyama ,  Kiyoo Itoh ,  Takeshi Sakata ,  Masakazu Aoki ,  Takayuki Kawahara

    发明人： Masashi Horiguchi ,  Kunio Uchiyama ,  Kiyoo Itoh ,  Takeshi Sakata ,  Masakazu Aoki ,  Takayuki Kawahara

    IPC分类号： G06F1/32

    CPC分类号： H01L27/0207 ,  G06F1/3203 ,  G11C5/14 ,  H01L27/0218 ,  H03K3/356113 ,  H03K19/0013 ,  H03K19/0016 ,  H03K19/01721

    摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

    摘要翻译： 半导体集成电路器件由各自设置有至少两个MOS晶体管的逻辑门组成。 逻辑门连接到第一电势点和第二电位点。 半导体集成电路装置包括连接在逻辑门与第一电位点之间和/或逻辑门与第二电势点之间的电流控制装置，用于根据操作状态控制在逻辑门中流动的电流的值 逻辑门。 该电路可用于在高功耗模式和低功耗模式之间循环运行的器件，例如具有用于功率降低的操作模式和低功率备用或睡眠模式的微处理器。

    Semiconductor integrated circuit device having power reduction mechanism
    9.
    发明授权
    Semiconductor integrated circuit device having power reduction mechanism 失效
    具有降压机构的半导体集成电路装置

    公开(公告)号：US07312640B2

    公开(公告)日：2007-12-25

    申请号：US11131181

    申请日：2005-05-18

    申请人： Masashi Horiguchi ,  Kunio Uchiyama ,  Kiyoo Itoh ,  Takeshi Sakata ,  Masakazu Aoki ,  Takayuki Kawahara

    发明人： Masashi Horiguchi ,  Kunio Uchiyama ,  Kiyoo Itoh ,  Takeshi Sakata ,  Masakazu Aoki ,  Takayuki Kawahara

    IPC分类号： H03K19/20

    CPC分类号： H01L27/0207 ,  G06F1/3203 ,  G11C5/14 ,  H01L27/0218 ,  H03K3/356113 ,  H03K19/0013 ,  H03K19/0016 ,  H03K19/01721

    摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

    摘要翻译： 半导体集成电路器件由各自设置有至少两个MOS晶体管的逻辑门组成。 逻辑门连接到第一电势点和第二电位点。 半导体集成电路装置包括连接在逻辑门与第一电位点之间和/或逻辑门与第二电势点之间的电流控制装置，用于根据操作状态控制在逻辑门中流动的电流的值 逻辑门。 该电路可用于在高功耗模式和低功耗模式之间循环运行的器件，例如具有用于功率降低的操作模式和低功率备用或睡眠模式的微处理器。