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公开(公告)号：US5880604A
公开(公告)日：1999-03-09
申请号：US714994
申请日：1996-09-17
申请人： Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
发明人： Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
IPC分类号： H01L27/00 , H01L27/02 , H03K3/356 , H03K19/00 , H03K19/094 , H03K19/20 , H03K19/0948 , H03K19/096
CPC分类号： H03K3/356113 , H03K19/0016 , H01L27/0218
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.
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公开(公告)号：US6107836A
公开(公告)日：2000-08-22
申请号：US199199
申请日：1998-11-25
申请人： Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
发明人： Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
CPC分类号： H03K3/356113 , H03K19/0016 , H01L27/0218
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.
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3.发明授权公开(公告)号：US06404239B1
公开(公告)日：2002-06-11
申请号：US09613594
申请日：2000-07-10
申请人： Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
发明人： Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
IPC分类号： H03K1920
CPC分类号： H03K3/356113 , H01L27/0218 , H03K19/0016
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.
摘要翻译： 半导体集成电路器件由各自设置有至少两个MOS晶体管的逻辑门组成。 逻辑门连接到第一电势点和第二电位点。 半导体集成电路装置包括连接在逻辑门与第一电位点之间和/或逻辑门与第二电势点之间的电流控制装置，用于根据操作状态控制在逻辑门中流动的电流的值 逻辑门。 该电路可用于在高功耗模式和低功耗模式之间循环运行的器件，例如具有用于功率降低的操作模式和低功率备用或睡眠模式的微处理器。
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4.发明授权
公开(公告)号：US5614847A
公开(公告)日：1997-03-25
申请号：US294055
申请日：1994-08-24
申请人： Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
发明人： Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
IPC分类号： H01L27/00 , H01L27/02 , H03K3/356 , H03K19/00 , H03K19/094 , H03K19/20 , H03K19/0948
CPC分类号： H03K3/356113 , H03K19/0016 , H01L27/0218
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.
摘要翻译： 半导体集成电路器件由各自设置有至少两个MOS晶体管的逻辑门组成。 逻辑门连接到第一电势点和第二电位点。 半导体集成电路装置包括连接在逻辑门与第一电位点之间和/或逻辑门与第二电势点之间的电流控制装置，用于根据操作状态控制在逻辑门中流动的电流的值 逻辑门。 该电路可用于在高功耗模式和低功耗模式之间循环运行的器件，例如具有用于功率降低的操作模式和低功率备用或睡眠模式的微处理器。
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公开(公告)号：US08106677B2
公开(公告)日：2012-01-31
申请号：US12844048
申请日：2010-07-27
IPC分类号： H03K19/003
CPC分类号： H04L25/0298 , G06F13/4072 , G06F13/4086 , H04B3/02 , H04L25/0278 , H04L25/028 , H04L25/0292 , H05K1/0216 , H05K1/0237 , H05K1/14
摘要： A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between the driving and receiving circuit blocks. The inter-block transmission line is terminated by a resistor having substantially the same impedance as the interblock transmission line. The intra-block transmission lines are provided with a resistance element having a resistance substantially equal to a value derived by subtracting half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.
摘要翻译： 信号发送电路包括具有用于发送来自驱动电路的信号的驱动电路和块内传输线路的电路块，具有接收电路的电路块和用于将信号发送到所述接收电路的块内传输线路 以及用于在驱动和接收电路块之间传播信号的主块间传输线。 块间传输线由具有与块间传输线基本上相同阻抗的电阻端接。 块内传输线路设置有电阻元件，其电阻基本上等于通过将块间传输线路的阻抗的一半从块内传输线路的阻抗减去一半到更低的信号幅度， 抑制沿着主块间传输线的分支点处的信号的反射，从而实现高速信号传送。
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公开(公告)号：US6069793A
公开(公告)日：2000-05-30
申请号：US10185
申请日：1998-01-21
申请人： Takashi Maruyama , Akira Yamagiwa , Ryoichi Kurihara , Masakazu Sakaue , Yasuhiro Uemura , Mikihiro Tanaka
发明人： Takashi Maruyama , Akira Yamagiwa , Ryoichi Kurihara , Masakazu Sakaue , Yasuhiro Uemura , Mikihiro Tanaka
CPC分类号： G06F1/206 , G06F1/20 , G06F1/203 , H01L23/36 , H01L2224/05599 , H01L2224/16225 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2224/85399 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2924/00014 , H01L2924/01079 , H01L2924/10253 , H01L2924/15311 , H01L2924/19105 , H01L2924/3025
摘要： The present invention provides an information processing apparatus that may be designed in small and thin size and a small and thin CPU module that has a nigh heat releasing effect and is suitable therefor. The CPU module includes a processor, a connector to be electrically connected to the outside, a system control circuit for controlling transfer of a signal between the processor and the connector, and a printed board on which the processor, the connector and the system control circuit are mounted. The CPU module further provides a heat release plate one side of which is pasted with the printed board and the other side of which is substantially planar. The printed board has a cavity formed therein so that the processor may be fitted in the cavity in a bare-chip state. One side of the bare chip is jointed with the heat release plate.
摘要翻译： 本发明提供一种可以设计成小型和小型的信息处理设备，以及具有最佳散热效果并且适合的小型和薄型CPU模块。 CPU模块包括处理器，电连接到外部的连接器，用于控制处理器和连接器之间的信号传送的系统控制电路，以及印刷电路板，处理器，连接器和系统控制电路 被安装。 CPU模块还提供一个散热片，其一面与印刷电路板粘贴，另一侧基本上是平面的。 印刷板具有形成在其中的空腔，使得处理器可以以裸芯片状态装配在空腔中。 裸芯片的一侧与散热板接合。
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公开(公告)号：US07911224B2
公开(公告)日：2011-03-22
申请号：US12116541
申请日：2008-05-07
IPC分类号： H03K19/003
CPC分类号： H04L25/0298 , G06F13/4072 , G06F13/4086 , H04B3/02 , H04L25/0278 , H04L25/028 , H04L25/0292 , H05K1/0216 , H05K1/0237 , H05K1/14
摘要： A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between the driving and receiving circuit blocks. The inter-block transmission line is terminated by a resistor having substantially the same impedance as the interblock transmission line. The intra-block transmission lines are provided with a resistance element having a resistance substantially equal to a value derived by subtracting half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.
摘要翻译： 信号发送电路包括具有用于发送来自驱动电路的信号的驱动电路和块内传输线路的电路块，具有接收电路的电路块和用于将信号发送到所述接收电路的块内传输线路 以及用于在驱动和接收电路块之间传播信号的主块间传输线。 块间传输线由具有与块间传输线基本上相同阻抗的电阻端接。 块内传输线路设置有电阻元件，其电阻基本上等于通过将块间传输线路的阻抗的一半从块内传输线路的阻抗减去一半到更低的信号幅度， 抑制沿着主块间传输线的分支点处的信号的反射，从而实现高速信号传送。
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公开(公告)号：US07123048B2
公开(公告)日：2006-10-17
申请号：US11049663
申请日：2005-02-04
IPC分类号： H03K17/16
CPC分类号： H04L25/0298 , G06F13/4072 , G06F13/4086 , H04B3/02 , H04L25/0278 , H04L25/028 , H04L25/0292 , H05K1/0216 , H05K1/0237 , H05K1/14
摘要： A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between the driving and receiving circuit blocks. The inter-block transmission line is terminated by a resistor having substantially the same impedance as the interblock transmission line. The intra-block transmission lines are provided with a resistance element having a resistance substantially equal to a value derived by subtracting half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.
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公开(公告)号：US20050088200A1
公开(公告)日：2005-04-28
申请号：US10989279
申请日：2004-11-17
IPC分类号： G06F3/00 , G06F12/00 , G06F13/16 , G06F13/40 , G11C11/401 , H03K19/0175 , H04B3/02 , H04L25/02 , H05K1/02 , H05K1/14 , H03K19/003
CPC分类号： H04L25/0298 , G06F13/4072 , G06F13/4086 , H04B3/02 , H04L25/0278 , H04L25/028 , H04L25/0292 , H05K1/0216 , H05K1/0237 , H05K1/14
摘要： A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between the driving and receiving circuit blocks. The inter-block transmission line is terminated by a resistor having substantially the same impedance as the interblock transmission line. The intra-block transmission lines are provided with a resistance element having a resistance substantially equal to a value derived by subtracting half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.
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10.再颁专利公开(公告)号：USRE38379E1
公开(公告)日：2004-01-06
申请号：US08184070
申请日：1994-01-21
申请人： Kouji Hara , Ryoichi Kurihara
发明人： Kouji Hara , Ryoichi Kurihara
IPC分类号： G11C804
CPC分类号： G11C7/222 , G11C5/066 , G11C7/22 , G11C8/18 , G11C11/406 , G11C11/4076 , G11C11/408
摘要： The semiconductor memory receives an external clock signal and has the memory cell array access operation controlled based on the clock signal. In the application of this semiconductor memory to a dynamic RAM, for example, a row address and column address are introduced in synchronism with the clock signal. The read, write and refresh operations are controlled based on the clock signal.
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