发明授权
- 专利标题： Semiconductor device having a multilevel interconnection structure
- 专利标题（中）： 具有多层互连结构的半导体器件
-
申请号： US827411申请日： 1997-03-27
-
公开(公告)号： US5952723A公开(公告)日： 1999-09-14
- 发明人: Nobuyuki Takeyasu , Hiroshi Yamamoto , Yumiko Kawano , Eiichi Kondoh , Tomoharu Katagiri , Tomohiro Ohta
- 申请人： Nobuyuki Takeyasu , Hiroshi Yamamoto , Yumiko Kawano , Eiichi Kondoh , Tomoharu Katagiri , Tomohiro Ohta
- 申请人地址： JPX Kobe
- 专利权人： Kawasaki Steel Corporation
- 当前专利权人： Kawasaki Steel Corporation
- 当前专利权人地址： JPX Kobe
- 优先权： JPX4-346838 19921225; JPX5-010078 19930125; JPX5-140883 19930611; JPX5-146430 19930617
- 主分类号： H01L21/768
- IPC分类号： H01L21/768 ; H01L23/522 ; H01L23/532 ; H01L23/48
摘要：
A semiconductor device has a multilevel interconnection structure that includes an insulating interlayer formed on a lower wiring layer, a semiconductor substrate, and at least one via hole. The via plug partially fills the via hole, and the upper surface of the via plug may have a convex shape or a surface of the lower wiring layer at a bottom of the via hole may have a concave shape. Where two via holes are present, one via plug substantially fills the shallowest via hole, and partially fills the deepest via hole. The upper wiring layer may be formed over the via plug to fill a remaining portion of the via hole not filled by the via plug.