公开(公告)号：US5637534A

公开(公告)日：1997-06-10

申请号：US172717

申请日：1993-12-27

申请人： Nobuyuki Takeyasu ,  Hiroshi Yamamoto ,  Yumiko Kawano ,  Eiichi Kondoh ,  Tomoharu Katagiri ,  Tomohiro Ohta

发明人： Nobuyuki Takeyasu ,  Hiroshi Yamamoto ,  Yumiko Kawano ,  Eiichi Kondoh ,  Tomoharu Katagiri ,  Tomohiro Ohta

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44

CPC分类号： H01L23/53223 ,  H01L21/76802 ,  H01L21/76879 ,  H01L23/5226 ,  H01L2924/0002

摘要： A semiconductor device has a multilayered structure that includes an insulating interlayer formed on a lower wiring layer, a semiconductor substrate, and a via hole. The semiconductor device is manufactured by a method that includes plasma etching at least one surface of the insulating interlayer the in an atmosphere having as a major component either a carbonless, chlorine-based gas or a carbonless, chlorine-based gas and an inactive gas in order to remove contaminates that would otherwise promote reactivity with aluminum CVD on the surface of the insulating interlayer.

摘要翻译： 半导体器件具有多层结构，其包括形成在下布线层，半导体衬底和通孔上的绝缘中间层。 半导体器件通过以下方法制造：包括在作为主要成分的无碳，氯系气体或无碳，氯系气体和惰性气体的气氛中等离子体蚀刻绝缘夹层的至少一个表面 以去除否则将促进绝缘中间层表面上的铝CVD的反应性的污染物。

公开(公告)号：US5952723A

公开(公告)日：1999-09-14

申请号：US827411

申请日：1997-03-27

申请人： Nobuyuki Takeyasu ,  Hiroshi Yamamoto ,  Yumiko Kawano ,  Eiichi Kondoh ,  Tomoharu Katagiri ,  Tomohiro Ohta

发明人： Nobuyuki Takeyasu ,  Hiroshi Yamamoto ,  Yumiko Kawano ,  Eiichi Kondoh ,  Tomoharu Katagiri ,  Tomohiro Ohta

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L23/53223 ,  H01L21/76802 ,  H01L21/76879 ,  H01L23/5226 ,  H01L2924/0002

摘要： A semiconductor device has a multilevel interconnection structure that includes an insulating interlayer formed on a lower wiring layer, a semiconductor substrate, and at least one via hole. The via plug partially fills the via hole, and the upper surface of the via plug may have a convex shape or a surface of the lower wiring layer at a bottom of the via hole may have a concave shape. Where two via holes are present, one via plug substantially fills the shallowest via hole, and partially fills the deepest via hole. The upper wiring layer may be formed over the via plug to fill a remaining portion of the via hole not filled by the via plug.

摘要翻译： 半导体器件具有多层互连结构，其包括形成在下布线层，半导体衬底和至少一个通孔上的绝缘夹层。 通孔插头部分地填充通孔，并且通孔插塞的上表面可以具有凸形形状，或者在通孔的底部的下布线层的表面可以具有凹形。 当存在两个通孔时，一个通孔插塞基本上填满最浅的通孔，并且部分填充最深的通孔。 上部布线层可以形成在通孔塞上，以填充未由通孔插塞填充的通孔的剩余部分。

公开(公告)号：US5627102A

公开(公告)日：1997-05-06

申请号：US569319

申请日：1995-12-08

申请人： Hiroshi Shinriki ,  Takeshi Kaizuka ,  Nobuyuki Takeyasu ,  Tomohiro Ohta ,  Eiichi Kondoh ,  Hiroshi Yamamoto ,  Tomoharu Katagiri ,  Tadashi Nakano ,  Yumiko Kawano

发明人： Hiroshi Shinriki ,  Takeshi Kaizuka ,  Nobuyuki Takeyasu ,  Tomohiro Ohta ,  Eiichi Kondoh ,  Hiroshi Yamamoto ,  Tomoharu Katagiri ,  Tadashi Nakano ,  Yumiko Kawano

IPC分类号： H01L21/285 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/28

CPC分类号： H01L21/76838 ,  H01L21/28556 ,  H01L21/32136 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/53223 ,  H01L2924/0002

摘要： A metal interconnection is prepared by forming an underlying metal film of high melting point metal such as Ti and/or high melting point metal compound such as TiN layers above a semiconductor substrate, plasma etching the surface of the underlying metal film in a gas atmosphere containing chloride, and forming an interconnecting metal film such as Al, Cu, Au and Ag on the underlying metal film. Alternatively, a metal interconnection is prepared by forming an insulating film above a semiconductor substrate, forming connection holes in the insulating film, forming an underlying metal film such as TiN on the insulating film and the bottom and side wall of the connection holes by a CVD process under controlled conditions, and forming an interconnecting metal film such as Al on the underlying metal film. The TiN film has (111) preferential orientation and the aluminum film has (111) preferential orientation, smooth surface and effective coverage. The thus fabricated metal interconnection has improved reliability including electromigration immunity when used in semiconductor devices and finding advantageous use in miniaturized semiconductor devices.

摘要翻译： 通过在半导体衬底之上形成诸如Ti和/或高熔点金属化合物如TiN层的高熔点金属的下面的金属膜，在等离子体中蚀刻下面的金属膜的表面，在含有 并在下面的金属膜上形成诸如Al，Cu，Au和Ag的互连金属膜。 或者，通过在半导体衬底上形成绝缘膜，在绝缘膜上形成连接孔，通过CVD在绝缘膜上形成TiN等下面的金属膜，形成连接孔的底壁和侧壁，形成金属互连 在控制条件下进行处理，并在底层金属膜上形成互连金属膜如Al。 TiN膜具有（111）优先取向，铝膜具有（111）优先取向，表面光滑，有效覆盖。 如此制造的金属互连具有改进的可靠性，包括当用于半导体器件中的电迁移抗扰性并且在小型化的半导体器件中发现有利的用途。

公开(公告)号：US06063703A

公开(公告)日：2000-05-16

申请号：US81047

申请日：1998-05-19

申请人： Hiroshi Shinriki ,  Takeshi Kaizuka ,  Nobuyuki Takeyasu ,  Tomohiro Ohta ,  Eiichi Kondoh ,  Hiroshi Yamamoto ,  Tomoharu Katagiri ,  Tadashi Nakano ,  Yumiko Kawano

发明人： Hiroshi Shinriki ,  Takeshi Kaizuka ,  Nobuyuki Takeyasu ,  Tomohiro Ohta ,  Eiichi Kondoh ,  Hiroshi Yamamoto ,  Tomoharu Katagiri ,  Tadashi Nakano ,  Yumiko Kawano

IPC分类号： H01L21/285 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76838 ,  H01L21/28556 ,  H01L21/32136 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/53223 ,  H01L2924/0002

摘要： A metal interconnection is prepared by forming an underlying metal film of high melting point metal such as Ti and/or high melting point metal compound such as TiN layers above a semiconductor substrate, plasma etching the surface of the underlying metal film in a gas atmosphere containing chloride, and forming an interconnecting metal film such as Al, Cu, Au and Ag on the underlying metal film. Alternatively, a metal interconnection is prepared by forming an insulating film above a semiconductor substrate, forming connecting holes in the insulating film, forming an underlying metal film such as TiN on the insulating film and the bottom and side wall of the connection holes by a CVD process under controlled conditions, and forming an interconnecting metal film such as Al on the underlying metal film. The TiN film has (111) preferential orientation and the aluminum film has (111) preferential orientation, smooth surface and effective coverage. The thus fabricated metal interconnection has improved reliability including electromigration immunity when used in semiconductor devices and finding advantageous use in miniaturized semiconductor devices.

摘要翻译： 通过在半导体衬底之上形成诸如Ti和/或高熔点金属化合物如TiN层的高熔点金属的下面的金属膜，在等离子体中蚀刻下面的金属膜的表面，在含有 并在下面的金属膜上形成诸如Al，Cu，Au和Ag的互连金属膜。 或者，通过在半导体衬底上形成绝缘膜，在绝缘膜上形成连接孔，在绝缘膜上形成诸如TiN的下面的金属膜和连接孔的底壁和侧壁，通过CVD 在控制条件下进行处理，并在底层金属膜上形成互连金属膜如Al。 TiN膜具有（111）优先取向，铝膜具有（111）优先取向，表面光滑，有效覆盖。 如此制造的金属互连具有改进的可靠性，包括当用于半导体器件中的电迁移抗扰性并且在小型化的半导体器件中发现有利的用途。

公开(公告)号：US5973402A

公开(公告)日：1999-10-26

申请号：US791161

申请日：1997-01-30

申请人： Hiroshi Shinriki ,  Takeshi Kaizuka ,  Nobuyuki Takeyasu ,  Tomohiro Ohta ,  Eiichi Kondoh ,  Hiroshi Yamamoto ,  Tomoharu Katagiri ,  Tadashi Nakano ,  Yumiko Kawano

发明人： Hiroshi Shinriki ,  Takeshi Kaizuka ,  Nobuyuki Takeyasu ,  Tomohiro Ohta ,  Eiichi Kondoh ,  Hiroshi Yamamoto ,  Tomoharu Katagiri ,  Tadashi Nakano ,  Yumiko Kawano

IPC分类号： H01L21/285 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76838 ,  H01L21/28556 ,  H01L21/32136 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/53223 ,  H01L2924/0002

摘要： A metal interconnection is prepared by forming an underlying metal film of high melting point metal such as Ti and/or high melting point metal compound such as TiN layers above a semiconductor substrate, plasma etching the surface of the underlying metal film in a gas atmosphere containing chloride, and forming an interconnecting metal film such as Al, Cu, Au and Ag on the underlying metal film. Alternatively, a metal interconnection is prepared by forming an insulating film above a semiconductor substrate, forming connection holes in the insulating film, forming an underlying metal film such as TiN on the insulating film and the bottom and side wall of the connection holes by a CVD process under controlled conditions, and forming an interconnecting metal film such as Al on the underlying metal film. The TiN film has (111) preferential orientation and the aluminum film has (111) preferential orientation, smooth surface and effective coverage. The thus fabricated metal interconnection has improved reliability including electromigration immunity when used in semiconductor devices and finding advantageous use in miniaturized semiconductor devices.

摘要翻译： 通过在半导体衬底之上形成诸如Ti和/或高熔点金属化合物如TiN层的高熔点金属的下面的金属膜，在等离子体中蚀刻下面的金属膜的表面，在含有 并在下面的金属膜上形成诸如Al，Cu，Au和Ag的互连金属膜。 或者，通过在半导体衬底上形成绝缘膜，在绝缘膜上形成连接孔，通过CVD在绝缘膜上形成TiN等下面的金属膜，形成连接孔的底壁和侧壁，形成金属互连 在控制条件下进行处理，并在底层金属膜上形成互连金属膜如Al。 TiN膜具有（111）优先取向，铝膜具有（111）优先取向，表面光滑，有效覆盖。 如此制造的金属互连具有改进的可靠性，包括当用于半导体器件中的电迁移抗扰性并且在小型化的半导体器件中发现有利的用途。

公开(公告)号：US5290736A

公开(公告)日：1994-03-01

申请号：US764901

申请日：1991-09-24

申请人： Nobuyoshi Sato ,  Kyoji Tokunaga ,  Tomoharu Katagiri ,  Tsuyoshi Hashimoto ,  Tomohiro Ohta

发明人： Nobuyoshi Sato ,  Kyoji Tokunaga ,  Tomoharu Katagiri ,  Tsuyoshi Hashimoto ,  Tomohiro Ohta

IPC分类号： C23C16/40 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L21/02164 ,  C23C16/402 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/31612 ,  Y10S148/118

摘要： A silicon oxide film to be used as an interlayer-insulating film in a semiconductor device is formed by a high pressure organic silane-O.sub.3 CVD. A semiconductor wafer is placed in a reaction vessel and is heated at a temperature of 350.degree. C. A mixture of an organic silane gas such as TEOS, HMDS and OMCTS and an ozone gas is introduced into the reaction vessel and the reaction is carried out at a pressure higher than the atmospheric pressure, preferably at a pressure of about 2 atm to form a silicon oxide film having excellent properties. A life time of the ozone gas which serves as an oxiding agent and/or catalyst can be prolonged under the high pressure, and therefore a deposition rate of the silicon oxide film ca be increased and the flatness of the silicon oxide film can be improved. Therefore, the silicon oxide film forming process can be performed efficiently and a flatening process after the formation of the silicon oxide film can be made simpler.

摘要翻译： 在半导体器件中用作层间绝缘膜的氧化硅膜通过高压有机硅烷-O 3 CVD形成。 将半导体晶片放置在反应容器中并在350℃的温度下加热。将有机硅烷气体如TEOS，HMDS和OMCTS与臭氧气体的混合物引入反应容器中，并进行反应 在高于大气压的压力下，优选在约2atm的压力下形成具有优异性能的氧化硅膜。 用作氧化剂和/或催化剂的臭氧气体的寿命可以在高压下延长，因此氧化硅膜的沉积速率可以提高，并且可以提高氧化硅膜的平坦度。 因此，可以有效地进行氧化硅膜形成工艺，并且可以使形成氧化硅膜之后的平坦化处理更简单。

公开(公告)号：US07087974B2

公开(公告)日：2006-08-08

申请号：US10773213

申请日：2004-02-09

申请人： Isamu Kuno ,  Tomoharu Katagiri

发明人： Isamu Kuno ,  Tomoharu Katagiri

IPC分类号： H01L29/76

CPC分类号： H01L21/76202 ,  G11C17/18 ,  H01L23/5252 ,  H01L27/0617 ,  H01L2924/0002 ,  H01L2924/00

摘要： An anti-fuse is manufactured by forming an isolation region including an insulating material layer buried in a surface of a device formation region on a surface of a semiconductor substrate, and by forming diffusion regions at both sides of the isolation region, then by contacting electrodes to the respective diffusion regions. The anti-fuse is initially in a non-conductive state, and is programmed to be in a permanently conductive state by a simple writing circuit.

摘要翻译： 通过在半导体衬底的表面上形成包括掩埋在器件形成区域的表面中的绝缘材料层的隔离区域，并且通过在隔离区域的两侧形成扩散区域来制造反熔丝， 到各个扩散区域。 反熔丝最初处于非导通状态，并通过简单的写入电路被编程为处于永久导通状态。