A high speed MOS device has a scaled channel length and integrated spacers. The MOS device is formed on a substrate having active and isolation regions. In constructing the MOS device wells and Vt regions are formed as required. Then, a thin nitride layer is formed upon the substrate. Subsequently, an oxide layer is formed upon the nitride layer. Then, the oxide layer is pattern masked to expose gate regions. The gate regions are sloped etched to form slope etched voids. The slope etching may proceed to the nitride layer, through a portion of the nitride layer or fully through the nitride layer, depending upon the embodiment. In another embodiment, the nitride layer is not deposed and the oxide layer is either fully or partially slope etched to the silicon substrate. The patterned mask is then removed and remaining portions of the nitride layer may be converted to an oxynitride. Additionally, a gate oxide may be formed. The slope etched void is then filled with a gate conductor and the surface is planarized in a CMP process. The gate conductor then has a shape wherein its lower surface is smaller than its upper surface. Then, the substrate is isotropically etched to remove portions of the oxide layer and nitride layer unprotected by the gate conductor. The remaining structure includes integrally formed spacers. Active regions, LDD regions and punchthrough regions are then formed to complete formation of the transistor.