A pipeline apparatus for processing 3D graphics data will be described. The pipeline apparatus includes a first request memory to fetch information corresponding to a texture operand. A second request memory fetches information responding to a color operand and Z operand. A control circuit coordinates data flow from the first request memory and the second request memory into a memory channel by preventing the number of requests from the first request memory from exceeding by a predetermined number, the number of requests from the second request memory. By properly coordinating the data flow, deadlock of a data fetching pipeline is avoided.