公开(公告)号：US07050063B1

公开(公告)日：2006-05-23

申请号：US09502994

申请日：2000-02-11

申请人： Michael Mantor ,  John Austin Carey ,  Ralph Clayton Taylor ,  Thomas A. Piazza ,  Jeffrey D. Potter ,  Angel E. Socarras

发明人： Michael Mantor ,  John Austin Carey ,  Ralph Clayton Taylor ,  Thomas A. Piazza ,  Jeffrey D. Potter ,  Angel E. Socarras

IPC分类号： G09G5/00

CPC分类号： G09G5/39 ,  G06T1/60 ,  G06T15/04 ,  G09G3/003 ,  G09G2360/121

摘要： A 3D rendering texture caching scheme that minimizes external bandwidth requirements for texture and increases the rate at which textured pixels are available. The texture caching scheme efficiently pre-fetches data at the main memory access granularity and stores it in cache memory. The data in the main memory and texture cache memory is organized in a manner to achieve large reuse of texels with a minimum of cache memory to minimize cache misses. The texture main memory stores a two dimensional array of texels, each texel having an address and one of N identifiers. The texture cache memory has addresses partitioned into N banks, each bank containing texels transferred from the main memory that have the corresponding identifier. A cache controller determines which texels need to be transferred from the texture main memory to the texture cache memory and which texels are currently in the cache using a least most recently used algorithm. By labeling the texture map blocks (double quad words), a partitioning scheme is developed which allow the cache controller structure to be very modular and easily realized. The texture cache arbiter is used for scheduling and controlling the actual transfer of texels from the texture main memory into the texture cache memory and controlling the outputting of texels for each pixel to an interpolating filter from the cache memory.

摘要翻译： 3D渲染纹理缓存方案，可最大限度地减少纹理的外部带宽需求，并提高纹理像素可用的速率。 纹理缓存方案有效地预取主存储器访问粒度的数据并将其存储在高速缓冲存储器中。 主存储器和纹理高速缓冲存储器中的数据被组织成以最小的高速缓冲存储器实现大量的纹理复用的重用，以最小化高速缓存未命中。 纹理主存储器存储纹素的二维阵列，每个纹素具有地址和N个标识符之一。 纹理高速缓冲存储器具有分割成N个存储体的地址，每个存储体包含从主存储器传送的具有相应标识符的纹素。 高速缓存控制器使用最近最少使用的算法来确定哪个纹素需要从纹理主存储器传送到纹理高速缓存存储器以及哪个纹素目前在高速缓存中。 通过标记纹理贴图块（双四字），开发了一种分区方案，允许高速缓存控制器结构非常模块化，轻松实现。 纹理高速缓存仲裁器用于调度和控制纹理主体存储器到纹理高速缓存存储器中的纹素的实际传输，并且控制从高速缓冲存储器输出每个像素的纹理像素到内插滤波器。

公开(公告)号：US6067090A

公开(公告)日：2000-05-23

申请号：US18773

申请日：1998-02-04

申请人： Aditya Sreenivas ,  Kam Leung ,  Sajjad Zaidi ,  Brian Rauchfuss ,  John Austin Carey ,  R. Scott Hartog ,  Michael Mantor

发明人： Aditya Sreenivas ,  Kam Leung ,  Sajjad Zaidi ,  Brian Rauchfuss ,  John Austin Carey ,  R. Scott Hartog ,  Michael Mantor

IPC分类号： G06T1/60 ,  G06T15/00 ,  G06F15/00

CPC分类号： G06T15/005 ,  G06T1/60

摘要： A pipeline apparatus for processing 3D graphics data will be described. The pipeline apparatus includes a first request memory to fetch information corresponding to a texture operand. A second request memory fetches information responding to a color operand and Z operand. A control circuit coordinates data flow from the first request memory and the second request memory into a memory channel by preventing the number of requests from the first request memory from exceeding by a predetermined number, the number of requests from the second request memory. By properly coordinating the data flow, deadlock of a data fetching pipeline is avoided.

摘要翻译： 将描述用于处理3D图形数据的流水线装置。 流水线装置包括用于获取与纹理操作数对应的信息的第一请求存储器。 第二个请求存储器提取响应颜色操作数和Z操作数的信息。 控制电路通过防止来自第一请求存储器的请求的数量超过预定数量来协调来自第一请求存储器和第二请求存储器的数据流到来自第二请求存储器的请求的数量。 通过适当地协调数据流，避免了数据获取管道的死锁。