发明授权
- 专利标题: Picture data recording and/or reproducing apparatus
- 专利标题(中): 图像数据记录和/或再现装置
-
申请号: US977748申请日: 1997-11-25
-
公开(公告)号: US6078723A公开(公告)日: 2000-06-20
- 发明人: Naofumi Yanagihara , Nobuaki Izumi
- 申请人: Naofumi Yanagihara , Nobuaki Izumi
- 申请人地址: JPX Tokyo
- 专利权人: Sony Corporation
- 当前专利权人: Sony Corporation
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX6-272193 19941107
- 主分类号: H04N5/783
- IPC分类号: H04N5/783 ; G11B20/10 ; H04N5/7826 ; H04N5/92 ; H04N5/93 ; H04N9/804 ; H04N9/877 ; H04N9/888 ; H04N19/102 ; H04N19/162 ; H04N19/167 ; H04N19/423 ; H04N19/44 ; H04N19/50 ; H04N19/503 ; H04N19/577 ; H04N19/61 ; H04N19/625 ; H04N19/70 ; H04N19/85 ; H04N19/91
摘要:
A recording/reproducing apparatus for reproducing recorded encoded picture data from a recording medium in varying speed without picture disruption. The recorded picture data are read from the recording medium and stored in a buffer memory. A detection circuit detects a picture header in the stored picture data and, depending upon the results of such detection, may or may not supply a clock signal therefrom. If a picture header is not detected, the detection circuit supplies the clock signal to the buffer memory and a delaying circuit. In response thereto, the stored picture data are read out from the buffer memory and supplied to the delaying circuit so as to be delayed by a predetermined amount prior to being supplied therefrom. If a picture header is detected during varying speed reproduction by the detection circuit, the clock signal is not supplied to the buffer memory and the delaying circuit, whereupon the delaying circuit outputs "0"s for a predetermined time period.
信息查询