发明授权
- 专利标题: Semiconductor device using complementary clock and signal input state detection circuit used for the same
- 专利标题(中): 半导体器件采用互补时钟和信号输入状态检测电路相同
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申请号: US76810申请日: 1998-05-13
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公开(公告)号: US6104225A公开(公告)日: 2000-08-15
- 发明人: Masao Taguchi , Yasurou Matsuzaki , Miki Yanagawa
- 申请人: Masao Taguchi , Yasurou Matsuzaki , Miki Yanagawa
- 申请人地址: JPX Kanagawa
- 专利权人: Fujitsu Limited
- 当前专利权人: Fujitsu Limited
- 当前专利权人地址: JPX Kanagawa
- 优先权: JPX9-103375 19970421; JPX10-059429 19980311
- 主分类号: G11C7/22
- IPC分类号: G11C7/22 ; H03K5/00 ; H03K5/135 ; H03K5/151 ; H03L7/081 ; G06F1/04
摘要:
A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180.degree. phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A 1/2 phase clock generating circuit generates a 1/2 phase shift signal 180.degree. out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the 1/2 phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.
公开/授权文献
- USD406053S Jewelry box 公开/授权日:1999-02-23