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129 条记录 (耗时 0.026 秒)

    Semiconductor device using complementary clock and signal input state detection circuit used for the same
    1.
    发明授权
    Semiconductor device using complementary clock and signal input state detection circuit used for the same 有权

    公开(公告)号：US06424199B1

    公开(公告)日：2002-07-23

    申请号：US09978022

    申请日：2001-10-17

    申请人： Masao Taguchi ,  Yasurou Matsuzaki ,  Miki Yanagawa

    发明人： Masao Taguchi ,  Yasurou Matsuzaki ,  Miki Yanagawa

    IPC分类号： H03K3013

    摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

    Semiconductor device using complementary clock and signal input state detection circuit used for the same
    3.
    发明授权
    Semiconductor device using complementary clock and signal input state detection circuit used for the same 有权

    公开(公告)号：US06225841B1

    公开(公告)日：2001-05-01

    申请号：US09556948

    申请日：2000-04-21

    申请人： Masao Taguchi ,  Yasurou Matsuzaki ,  Miki Yanagawa

    发明人： Masao Taguchi ,  Yasurou Matsuzaki ,  Miki Yanagawa

    IPC分类号： H03B1900

    CPC分类号： H03L7/0805 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03K5/135 ,  H03K5/151 ,  H03K2005/00234 ,  H03L7/0814

    摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

    Semiconductor device using complementary clock and signal input state detection circuit used for the same
    4.
    发明授权
    Semiconductor device using complementary clock and signal input state detection circuit used for the same 失效
    半导体器件采用互补时钟和信号输入状态检测电路相同

    公开(公告)号：US6104225A

    公开(公告)日：2000-08-15

    申请号：US76810

    申请日：1998-05-13

    申请人： Masao Taguchi ,  Yasurou Matsuzaki ,  Miki Yanagawa

    发明人： Masao Taguchi ,  Yasurou Matsuzaki ,  Miki Yanagawa

    IPC分类号： G11C7/22 ,  H03K5/00 ,  H03K5/135 ,  H03K5/151 ,  H03L7/081 ,  G06F1/04

    CPC分类号： H03L7/0805 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03K5/135 ,  H03K5/151 ,  H03K2005/00234 ,  H03L7/0814

    摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180.degree. phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A 1/2 phase clock generating circuit generates a 1/2 phase shift signal 180.degree. out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the 1/2 phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

    摘要翻译： 公开了一种半导体器件，用于从外部时钟产生彼此互补的第一和第二内部时钟，并且可用于使用互补时钟的系统和内部产生180°相位时钟的系统的系统。 第一时钟输入电路（缓冲器）被提供有第一外部时钟并输出第一内部时钟。 第二时钟输入电路（缓冲器）被提供有与第一外部时钟互补的第二外部时钟并输出第二时钟。 A + E，fra 1/2 + EE相位时钟发生电路产生与第一内部时钟异相180°的+ E，fra 1/2 + EE相移信号。 第二外部时钟状态检测电路判断第二外部时钟是否被输入到第二时钟输入缓冲器。 当第二外部时钟被输入时，开关被操作以产生第二时钟作为第二内部时钟，并且当第二外部时钟未被输入时产生+ E，fra 1/2 + EE相移信号作为第二内部时钟 ，根据第二外部时钟状态检测电路的判断。

    Semiconductor integrated circuit memory
    7.
    发明授权
    Semiconductor integrated circuit memory 有权
    半导体集成电路存储器

    公开(公告)号：US06185149B2

    公开(公告)日：2001-02-06

    申请号：US09340147

    申请日：1999-06-28

    申请人： Shinya Fujioka ,  Masao Taguchi ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Yasurou Matsuzaki ,  Toshiya Uchida

    发明人： Shinya Fujioka ,  Masao Taguchi ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Yasurou Matsuzaki ,  Toshiya Uchida

    IPC分类号： G11C800

    CPC分类号： G11C7/1018 ,  G11C7/1072

    摘要： A semiconductor memory includes memory cell blocks, a burst-length information generating circuit which generates burst-length information based on a burst length, and a block enable circuit which receives the burst-length information. The block enable circuit selectively enables one of the memory cell blocks when the burst length is equal to or shorter than a predetermined burst length and selectively enables a plurality of memory cell blocks based on the burst length when the burst length is longer than the predetermined burst length. Data are read from the above-mentioned one or plurality of memory cell blocks.

    摘要翻译： 半导体存储器包括存储单元块，基于突发长度生成突发长度信息的突发长度信息产生电路，以及接收脉冲串长度信息的块使能电路。 当突发长度等于或小于预定突发长度时，块使能电路选择性地启用存储单元块中的一个，并且当突发长度长于预定突发时，基于脉冲串长度选择性地启用多个存储单元块 长度。 从上述一个或多个存储单元块读取数据。

    Dynamic memory circuit with automatic refresh function
    10.
    发明授权
    Dynamic memory circuit with automatic refresh function 失效
    动态内存电路具有自动刷新功能

    公开(公告)号：US06438055B1

    公开(公告)日：2002-08-20

    申请号：US09688941

    申请日：2000-10-17

    申请人： Masao Taguchi ,  Yasurou Matsuzaki

    发明人： Masao Taguchi ,  Yasurou Matsuzaki

    IPC分类号： G11C700

    CPC分类号： G11C11/406

    摘要： The present invention is that in a dynamic memory circuit, first and second internal operation cycles are assigned to one external operation cycle according to external commands, a memory core performs a read operation which corresponds to a read command at the first internal operation, and performs a refresh operation which responds to a refresh command at the second internal operation cycle. Also the memory core performs a refresh operation which responds to a refresh command at the first internal operation cycle, and performs a write operation which corresponds to a write command at the second internal operation cycle. It is preferable that when the read or write command is not input, the refresh operation is performed at the earlier internal operation cycle. And a refresh command generation circuit which generates the refresh command at a refresh time is created in the memory circuit.

    摘要翻译： 本发明是在动态存储电路中，根据外部指令将第一和第二内部动作周期分配给一个外部动作周期，在第一内部动作中，存储器核心进行与读出命令对应的读取动作， 在第二内部操作周期响应刷新命令的刷新操作。 此外，存储器核心执行在第一内部操作周期响应刷新命令的刷新操作，并且在第二内部操作周期执行与写入命令相对应的写入操作。 优选的是，当没有输入读取或写入命令时，在较早的内部操作周期执行刷新操作。 并且在存储器电路中创建在刷新时间产生刷新命令的刷新命令产生电路。