发明授权
US06118697A Nonvolatile semiconductor memory in which the number of programming or
erasing bits increases with the progress of programming or erasing
有权
非易失性半导体存储器,其中编程或擦除位的数量随着编程或擦除的进行而增加
- 专利标题: Nonvolatile semiconductor memory in which the number of programming or erasing bits increases with the progress of programming or erasing
- 专利标题(中): 非易失性半导体存储器,其中编程或擦除位的数量随着编程或擦除的进行而增加
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申请号: US324775申请日: 1999-06-03
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公开(公告)号: US06118697A公开(公告)日: 2000-09-12
- 发明人: Tooru Tanzawa , Nobuaki Otsuka , Hironori Banba , Shigeru Atsumi , Masao Kuriyama , Seiichi Mori , Seiji Yamada
- 申请人: Tooru Tanzawa , Nobuaki Otsuka , Hironori Banba , Shigeru Atsumi , Masao Kuriyama , Seiichi Mori , Seiji Yamada
- 申请人地址: JPX Kawasaki
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JPX Kawasaki
- 优先权: JPX10-154504 19980603
- 主分类号: G11C16/02
- IPC分类号: G11C16/02 ; G11C16/04 ; G11C16/10 ; G11C16/14 ; G11C16/00
摘要:
A NOR type flash memory includes a plurality of word lines, a plurality of bit lines, at least one bit line, a plurality of nonvolatile memory cells, a row decoder, a cell selection circuit and a programming load. Each of the plurality of nonvolatile memory cells includes a gate electrode, drain electrode and source electrode and the gate electrode is connected to a corresponding one of the plurality of word lines, the drain electrode is connected to a corresponding one of the plurality of bit lines and the source electrode is connected to the source line. The row decoder selects one of the plurality of word lines at the time of data programming. The cell selection circuit includes a column decoder and column gates and is constructed to simultaneously select one bit line from each of the plurality of groups among the plurality of bit lines. The programming load increases the number of programming bits with the progress of programming when data of plural bits is programmed into a plurality of memory cells simultaneously selected by the cell selection circuit.
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