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    Nonvolatile semiconductor memory in which the number of programming or erasing bits increases with the progress of programming or erasing
    1.
    发明授权
    Nonvolatile semiconductor memory in which the number of programming or erasing bits increases with the progress of programming or erasing 失效
    非易失性半导体存储器，其中编程或擦除位的数量随着编程或擦除的进行而增加

    公开(公告)号：US06222773B1

    公开(公告)日：2001-04-24

    申请号：US09592661

    申请日：2000-06-13

    申请人： Tooru Tanzawa ,  Nobuaki Otsuka ,  Hironori Banba ,  Shigeru Atsumi ,  Masao Kuriyama ,  Seiichi Mori ,  Seiji Yamada

    发明人： Tooru Tanzawa ,  Nobuaki Otsuka ,  Hironori Banba ,  Shigeru Atsumi ,  Masao Kuriyama ,  Seiichi Mori ,  Seiji Yamada

    IPC分类号： G11C1600

    CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/14

    摘要： A NOR type flash memory includes a plurality of word lines, a plurality of bit lines, at least one bit line, a plurality of nonvolatile memory cells, a row decoder, a cell selection circuit and a programming load. Each of the plurality of nonvolatile memory cells includes a gate electrode, drain electrode and source electrode and the gate electrode is connected to a corresponding one of the plurality of word lines, the drain electrode is connected to a corresponding one of the plurality of bit lines and the source electrode is connected to the source line. The row decoder selects one of the plurality of word lines at the time of data programming. The cell selection circuit includes a column decoder and column gates and is constructed to simultaneously select one bit line from each of the plurality of groups among the plurality of bit lines. The programming load increases the number of programming bits with the progress of programming when data of plural bits is programmed into a plurality of memory cells simultaneously selected by the cell selection circuit.

    摘要翻译： NOR型闪速存储器包括多个字线，多个位线，至少一个位线，多个非易失性存储器单元，行解码器，单元选择电路和编程负载。 多个非易失性存储单元中的每一个包括栅电极，漏电极和源电极，并且栅电极连接到多个字线中的相应一个字线，漏极连接到多个位线中的相应一个位线 并且源极连接到源极线。 行解码器在数据编程时选择多个字线之一。 单元选择电路包括列解码器和列门，并被构造为从多个位线中的多个组中的每一个同时选择一个位线。 当多个位的数据被编程到由单元选择电路同时选择的多个存储单元中时，编程负载增加了编程进程的编程位数。

    Nonvolatile semiconductor memory in which the number of programming or erasing bits increases with the progress of programming or erasing
    2.
    发明授权
    Nonvolatile semiconductor memory in which the number of programming or erasing bits increases with the progress of programming or erasing 有权
    非易失性半导体存储器，其中编程或擦除位的数量随着编程或擦除的进行而增加

    公开(公告)号：US06118697A

    公开(公告)日：2000-09-12

    申请号：US324775

    申请日：1999-06-03

    申请人： Tooru Tanzawa ,  Nobuaki Otsuka ,  Hironori Banba ,  Shigeru Atsumi ,  Masao Kuriyama ,  Seiichi Mori ,  Seiji Yamada

    发明人： Tooru Tanzawa ,  Nobuaki Otsuka ,  Hironori Banba ,  Shigeru Atsumi ,  Masao Kuriyama ,  Seiichi Mori ,  Seiji Yamada

    IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/00

    CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/14

    摘要： A NOR type flash memory includes a plurality of word lines, a plurality of bit lines, at least one bit line, a plurality of nonvolatile memory cells, a row decoder, a cell selection circuit and a programming load. Each of the plurality of nonvolatile memory cells includes a gate electrode, drain electrode and source electrode and the gate electrode is connected to a corresponding one of the plurality of word lines, the drain electrode is connected to a corresponding one of the plurality of bit lines and the source electrode is connected to the source line. The row decoder selects one of the plurality of word lines at the time of data programming. The cell selection circuit includes a column decoder and column gates and is constructed to simultaneously select one bit line from each of the plurality of groups among the plurality of bit lines. The programming load increases the number of programming bits with the progress of programming when data of plural bits is programmed into a plurality of memory cells simultaneously selected by the cell selection circuit.

    摘要翻译： NOR型闪速存储器包括多个字线，多个位线，至少一个位线，多个非易失性存储器单元，行解码器，单元选择电路和编程负载。 多个非易失性存储单元中的每一个包括栅电极，漏电极和源电极，并且栅电极连接到多个字线中的相应一个字线，漏极连接到多个位线中的相应一个位线 并且源极连接到源极线。 行解码器在数据编程时选择多个字线之一。 单元选择电路包括列解码器和列门，并被构造为从多个位线中的多个组中的每一个同时选择一个位线。 当多个位的数据被编程到由单元选择电路同时选择的多个存储单元中时，编程负载增加了编程进程的编程位数。

    Non-volatile semiconductor memory device and data erasing method therefor
    3.
    发明授权
    Non-volatile semiconductor memory device and data erasing method therefor 失效
    非挥发性半导体存储器件及其数据擦除方法

    公开(公告)号：US5568419A

    公开(公告)日：1996-10-22

    申请号：US507968

    申请日：1995-07-27

    申请人： Shigeru Atsumi ,  Masao Kuriyama ,  Hironori Banba ,  Akira Umezawa ,  Nobuaki Otsuka

    发明人： Shigeru Atsumi ,  Masao Kuriyama ,  Hironori Banba ,  Akira Umezawa ,  Nobuaki Otsuka

    IPC分类号： G11C16/02 ,  G11C16/06 ,  G11C16/16 ,  G11C16/34 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

    CPC分类号： G11C16/3409 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3445

    摘要： A memory cell array has a plurality of memory cells formed of EEPROM cells arranged in a matrix form. Data in the memory cells is flash-erased, and after this, word lines other than a selected word line are set to a negative potential and erasing verification for detecting an insufficiently erased memory cell is effected. The flash-erasing and erasing verification are repeatedly effected until no insufficiently erased memory cell is detected. When no insufficiently erased memory cell is detected, word lines other than a selected word line are set to a negative potential and an overerased memory cell is detected. When an overerased memory cell is detected, weak program is effected for the cell by applying a voltage lower than the normal writing voltage to the cell.

    摘要翻译： 存储单元阵列具有以矩阵形式布置的EEPROM单元形成的多个存储单元。 存储器单元中的数据被闪存擦除，之后，除了所选字线之外的字线被设置为负电位，并且实现用于检测不充分擦除的存储器单元的擦除验证。 重复进行闪光擦除和擦除验证，直到没有检测到不充分擦除的存储单元。 当没有检测到不充分擦除的存储单元时，除了所选字线以外的字线被设置为负电位，并且检测到过高的存储单元。 当检测到过高的存储单元时，通过将低于正常写入电压的电压施加到单元来对单元进行弱程序。

    Semiconductor integrated circuit device with erasable and programmable fuse memory
    5.
    发明授权
    Semiconductor integrated circuit device with erasable and programmable fuse memory 失效
    具有可擦除和可编程保险丝存储器的半导体集成电路器件

    公开(公告)号：US06856543B2

    公开(公告)日：2005-02-15

    申请号：US10743385

    申请日：2003-12-23

    申请人： Shigeru Atsumi ,  Masao Kuriyama ,  Akira Umezawa ,  Hironori Banba ,  Tadayuki Taura ,  Hidetoshi Saito

    发明人： Shigeru Atsumi ,  Masao Kuriyama ,  Akira Umezawa ,  Hironori Banba ,  Tadayuki Taura ,  Hidetoshi Saito

    IPC分类号： G11C5/00 ,  G11C5/14 ,  G11C16/04 ,  H01L29/78 ,  H03K5/153 ,  H03K5/22

    CPC分类号： G11C5/143 ,  G11C5/14 ,  G11C7/1045 ,  G11C16/26 ,  G11C16/30

    摘要： A semiconductor integrated circuit device includes fuse cells arranged at a fuse cell array, a fuse cell data program and erase circuit, a fuse cell data control circuit, and fuse data latch circuits. The fuse cells include erasable and programmable nonvolatile memory cells. The fuse cell data program and erase circuit programs fuse data to the memory cells and erases the fuse data from the memory cells. The fuse cell data control circuit controls read out timing of the fuse data stored in the memory cells based on a signal generated upon detection of power-on. The fuse data latch circuits latch the fuse data read out from the memory cells.

    摘要翻译： 半导体集成电路器件包括设置在熔丝单元阵列处的熔丝单元，熔丝单元数据程序和擦除电路，熔丝单元数据控制电路和熔丝数据锁存电路。 熔丝单元包括可擦除和可编程的非易失性存储单元。 熔丝单元数据程序和擦除电路程序将数据熔化到存储单元，并从存储单元擦除熔丝数据。 熔丝单元数据控制电路基于在检测到通电时产生的信号来控制存储在存储单元中的熔丝数据的读出定时。 熔丝数据锁存电路锁存从存储器单元读出的熔丝数据。

    Semiconductor integrated circuit device with operation/function setting information memory
    8.
    发明授权
    Semiconductor integrated circuit device with operation/function setting information memory 失效
    具有操作/功能设定信息存储器的半导体集成电路器件

    公开(公告)号：US06700817B2

    公开(公告)日：2004-03-02

    申请号：US10265728

    申请日：2002-10-08

    申请人： Shigeru Atsumi ,  Masao Kuriyama ,  Akira Umezawa ,  Hironori Banba ,  Tadayuki Taura ,  Hidetoshi Saito

    发明人： Shigeru Atsumi ,  Masao Kuriyama ,  Akira Umezawa ,  Hironori Banba ,  Tadayuki Taura ,  Hidetoshi Saito

    IPC分类号： G11C1604

    CPC分类号： G11C5/143 ,  G11C5/14 ,  G11C7/1045 ,  G11C16/26 ,  G11C16/30

    摘要： A semiconductor integrated circuit device includes a nonvolatile memory cell, a source of the cell receiving a ground potential, and a gate of the cell receiving a first control signal; a transistor, a source of the transistor receiving a drain potential of the cell, and a gate of the transistor receiving a second control signal; and a controller. The controller receives a third control signal generated upon detection of power-on and outputs the first and second control signals. A potential of the first control signal changes from the ground potential to a potential different from the ground potential, which is maintained during a first period of time, and a potential of the second control signal changes from the ground potential to a potential different from the ground potential, which is maintained during a second period of time.

    摘要翻译： 半导体集成电路装置包括：非易失性存储单元，接收地电位的单元的源极和接收第一控制信号的单元的栅极; 晶体管，晶体管的源极，接收所述单元的漏极电位，以及所述晶体管的栅极接收第二控制信号; 和控制器。 控制器接收在检测到电源接通时产生的第三控制信号，并输出第一和第二控制信号。 第一控制信号的电位从接地电位变化到在第一时间段期间保持的接地电位不同的电位，并且第二控制信号的电位从地电势变为不同于 地电位，在第二段时间内保持。

    Semiconductor integrated circuit device
    9.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US06320428B1

    公开(公告)日：2001-11-20

    申请号：US09527582

    申请日：2000-03-17

    申请人： Shigeru Atsumi ,  Masao Kuriyama ,  Akira Umezawa ,  Hironori Banba ,  Tadayuki Taura ,  Hidetoshi Saito

    发明人： Shigeru Atsumi ,  Masao Kuriyama ,  Akira Umezawa ,  Hironori Banba ,  Tadayuki Taura ,  Hidetoshi Saito

    IPC分类号： H03K522

    CPC分类号： G11C5/143 ,  G11C5/14 ,  G11C7/1045 ,  G11C16/26 ,  G11C16/30

    摘要： A semiconductor integrated circuit device has a data storage section for storing mode setting data corresponding to products of a plurality of types, redundancy data, and so on. The redundancy storage section is made up of a nonvolatile transistor for storing the mode setting data corresponding to the products, the redundancy data, etc., a latch circuit for latching data read out from the nonvolatile transistor and generating a mode signal, and a transmission gate for transmitting the data from read out from the nonvolatile transistor to the latch circuit. The semiconductor integrated circuit device also has an internal voltage generator for generating an internal voltage. This internal voltage is used as the power supply voltage of the data storage section.

    摘要翻译： 半导体集成电路装置具有用于存储对应于多种类型，冗余数据等的产品的模式设置数据的数据存储部分。 冗余存储部分由用于存储对应于产品，冗余数据等的模式设置数据的非易失性晶体管，用于锁存从非易失性晶体管读出的数据并产生模式信号的锁存电路，以及传输 用于将从非易失性晶体管读出的数据发送到锁存电路。 半导体集成电路器件还具有用于产生内部电压的内部电压发生器。 该内部电压用作数据存储部分的电源电压。

    Nonvolatile semiconductor memory system
    10.
    发明授权
    Nonvolatile semiconductor memory system 失效
    非易失性半导体存储器系统

    公开(公告)号：US06160738A

    公开(公告)日：2000-12-12

    申请号：US181404

    申请日：1994-01-13

    申请人： Shigeru Atsumi ,  Hironori Banba ,  Masao Kuriyama

    发明人： Shigeru Atsumi ,  Hironori Banba ,  Masao Kuriyama

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/34 ,  G11C16/06

    CPC分类号： G11C16/3431 ,  G11C16/3418

    摘要： A nonvolatile semiconductor memory system is provided with a nonvolatile memory cell array divided into erase blocks data and refresh blocks, and a flag cell array including a plurality of nonvolatile flag cells each of which corresponds to one of the refresh blocks and stores data representing the refresh status of the corresponding refresh block.

    摘要翻译： 非易失性半导体存储器系统设置有被划分为擦除块数据和刷新块的非易失性存储单元阵列，以及包括多个非易失性标志单元的标志单元阵列，每个非易失性标志单元对应于一个刷新块，并存储表示刷新的数据 相应刷新块的状态。