An array of DRAM cells having cactus-shaped stacked capacitors with increased capacitance is achieved. A first planar insulating layer is formed, and a silicon nitride (Si.sub.3 N.sub.4) layer having openings over the FET source/drain areas for node contacts is formed. A thick third insulating layer is deposited and etched to form recesses over the openings for the bottom electrodes, and node contact openings are concurrently etched in the first insulating layer using the Si.sub.3 N.sub.4 as an etch-stop mask. A first polysilicon layer is deposited to fill the node contact openings and to conformally coat the recesses. A series of layers composed of a fourth insulating, a second polysilicon, and a fifth insulating layer is deposited, while retaining an opening in the recess. The layers in the series are sequentially etched back and then a third polysilicon layer is deposited and chem/mech polished back to the third insulating layer. The exposed insulating layers are then isotropically removed selectively to the Si.sub.3 N.sub.4 layer to form cactus-shaped capacitor bottom electrodes. The DRAM capacitors are then completed by forming an interelectrode dielectric layer and patterning a fourth polysilicon layer to form the top electrodes.