发明授权
- 专利标题: System including phase lock loop circuit
- 专利标题(中): 系统包括锁相环电路
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申请号: US966786申请日: 1997-11-10
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公开(公告)号: US6163186A公开(公告)日: 2000-12-19
- 发明人: Kozaburo Kurita
- 申请人: Kozaburo Kurita
- 申请人地址: JPX Tokyo
- 专利权人: Hitachi, Ltd.
- 当前专利权人: Hitachi, Ltd.
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX8-314226 19961111
- 主分类号: G06F1/10
- IPC分类号: G06F1/10 ; H03K3/0231 ; H03K3/354 ; H03L7/07 ; H03L7/089 ; H03L7/099 ; H03L7/10 ; H03L7/18 ; H03L7/06
摘要:
A PLL circuit includes a phase comparator which makes a comparison between an internal clock signal and a clock signal supplied from an external terminal, a charge pump circuit which produces a charging-up or discharging current in accordance with the output of the phase comparator, so as to drive a filter capacitor, a voltage-controlled oscillator the oscillation frequency of which is controlled by the held voltage of the filter capacitor, and a frequency divider circuit which generates the internal clock signal on the basis of the oscillation output of the voltage-controlled oscillator. The PLL circuit is additionally provided with a voltage detector circuit which detects whether the held voltage of the filter capacitor has been raised to a predetermined voltage or higher, and the function of forcibly lowering the held voltage of the filter capacitor down to a predetermined potential in accordance with the detection output of the voltage detector circuit. Besides, a system is provided with a detection and setting circuit which detects a state brought about by the electrical disconnection of the feedback loop of the PLL circuit, and which brings the PLL circuit into a predetermined state.
公开/授权文献
- US5245069A Process for the preparation of bis(aryl)-phosphorohalidates 公开/授权日:1993-09-14