发明授权
- 专利标题： Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same
- 专利标题（中）： 具有低介电常数绝缘体的芯片互连布线结构及其制造方法
-
申请号： US09715559申请日： 2000-11-17
-
公开(公告)号： US06577011B1公开(公告)日： 2003-06-10
- 发明人: Leena P. Buchwalter , Alessandro Cesare Callegari , Stephan Alan Cohen , Teresita Ordonez Graham , John P. Hummel , Christopher V. Jahnes , Sampath Purushothaman , Katherine Lynn Saenger , Jane Margaret Shaw
- 申请人： Leena P. Buchwalter , Alessandro Cesare Callegari , Stephan Alan Cohen , Teresita Ordonez Graham , John P. Hummel , Christopher V. Jahnes , Sampath Purushothaman , Katherine Lynn Saenger , Jane Margaret Shaw
- 主分类号： H01L2348
- IPC分类号： H01L2348
摘要：
The present invention includes a multilevel air-gap-containing interconnect wiring structure including: a collection of interspersed line levels and via levels, the via levels and line levels containing conductive via and line features embedded in a dielectric having an air-gap and solid dielectric. The air-gap and solid dielectric includes (i) one or more solid dielectrics only in the shadows of the conductive features in overlying levels and (ii) a gaseous dielectric elsewhere in the structure. The collection of line levels and via levels are topped by a laminated thin, taut insulating cover layer having openings to selected conductive features in the topmost underlying line or via layer, and the openings are filled with conductive material connecting to terminal pad contacts on the insulating cover layer.
信息查询
