公开(公告)号：US08247905B2

公开(公告)日：2012-08-21

申请号：US12538782

申请日：2009-08-10

申请人： Hariklia Deligianni ,  Qiang Huang ,  John P. Hummel ,  Lubomyr T. Romankiw ,  Mary B. Rothwell

发明人： Hariklia Deligianni ,  Qiang Huang ,  John P. Hummel ,  Lubomyr T. Romankiw ,  Mary B. Rothwell

IPC分类号： H01L29/40

CPC分类号： H01L21/76879 ,  H01L21/2885 ,  Y10S205/925

摘要： The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete metal contact pad located on the substrate surface, an inter-level dielectric (ILD) layer over both the discrete metal contact pad and the substrate, and a metal via structure extending through the ILD layer onto the discrete metal contact pad. Next, a vertical via is formed in the template structure, which extends through the ILD layer onto the discrete metal contact pad. A vertical conductive structure is then formed in the vertical via by electroplating, which is conducted by applying an electroplating current to the discrete metal contact pad through the metal via structure. Preferably, the template structure comprises multiple discrete metal contact pads, multiple metal via structures, and multiple vertical vias for formation of multiple vertical conductive structures.

摘要翻译： 本发明涉及通过电镀形成垂直导电结构的方法。 具体地，首先形成模板结构，其包括衬底，位于衬底表面上的离散金属接触焊盘，分立金属接触焊盘和衬底两者之间的级间电介质（ILD）层，以及金属通孔结构 延伸穿过ILD层到分立的金属接触垫上。 接下来，在模板结构中形成垂直通孔，其延伸穿过ILD层到分立的金属接触垫上。 然后通过电镀在垂直通孔中形成垂直导电结构，电镀通过通过金属通孔结构将电镀电流施加到离散的金属接触焊盘来进行。 优选地，模板结构包括多个分立的金属接触焊盘，多个金属通孔结构以及用于形成多个垂直导电结构的多个垂直通孔。

公开(公告)号：US07803639B2

公开(公告)日：2010-09-28

申请号：US11619623

申请日：2007-01-04

申请人： Solomon Assefa ,  Michael C. Gaidis ,  John P. Hummel ,  Sivananda K. Kanakasabapathy

发明人： Solomon Assefa ,  Michael C. Gaidis ,  John P. Hummel ,  Sivananda K. Kanakasabapathy

IPC分类号： H01L21/00 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L43/12 ,  H01L21/76807 ,  H01L21/76816

摘要： A method of forming vertical contacts in an integrated circuit that couple one or more metal lines in a given metallization level to first and second features occupying different levels in the integrated circuit comprises various processing steps. A first etch stop layer is formed overlying at least of portion of the first feature while a second etch stop layer is formed overlying at least a portion of the second feature. An ILD layer is formed overlying the first and second etch stop layers. A photolithographic mask is formed overlying the ILD layer. The photolithographic mask defines a first opening over the first feature and a second opening over the second feature. A first etch process etches a first hole in the ILD layer through the first opening in the photolithographic mask that lands on the first etch stop layer and etches a second hole in the ILD layer through the second opening that lands on the second etch stop layer. Subsequently, a second etch process further etches the first hole so that it lands on the first feature.

摘要翻译： 在集成电路中形成垂直触点的方法，其将给定金属化水平中的一个或多个金属线耦合到在集成电路中占据不同电平的第一和第二特征包括各种处理步骤。 形成第一蚀刻停止层，覆盖第一特征的至少一部分，而形成第二蚀刻停止层，覆盖第二特征的至少一部分。 形成覆盖在第一和第二蚀刻停止层上的ILD层。 在ILD层上形成光刻掩模。 光刻掩模限定第一特征上的第一开口和第二特征上的第二开口。 第一蚀刻工艺通过位于第一蚀刻停止层上的光刻掩模中的第一开口蚀刻ILD层中的第一孔，并通过第二开口蚀刻ILD层中的第二孔，该第二孔位于第二蚀刻停止层上。 随后，第二蚀刻工艺进一步蚀刻第一孔使其落在第一特征上。

公开(公告)号：US20080211055A1

公开(公告)日：2008-09-04

申请号：US12120915

申请日：2008-05-15

申请人： Solomon Assefa ,  Michael C. Gaidis ,  Sivananda Kanakasabapathy ,  John P. Hummel ,  David W. Abraham

发明人： Solomon Assefa ,  Michael C. Gaidis ,  Sivananda Kanakasabapathy ,  John P. Hummel ,  David W. Abraham

IPC分类号： H01L43/00 ,  H01L43/12

CPC分类号： H01L43/12 ,  H01L27/222

摘要： Novel methods for reliably and reproducibly forming magnetic tunnel junctions in integrated circuits are described. In accordance with aspects of the invention, sidewall spacer features are utilized during the processing of the film stack. Advantageously, these sidewall spacer features create a tapered masking feature which helps to avoid byproduct redeposition during the etching of the MTJ film stack, thereby improving process yield. Moreover, the sidewall spacer features may be used as encapsulating layers during subsequent processing steps and as vertical contacts to higher levels of metallization.

摘要翻译： 描述了在集成电路中可靠且可重复地形成磁隧道结的新方法。 根据本发明的方面，在膜叠层的处理期间利用侧壁间隔物特征。 有利地，这些侧壁间隔物特征产生锥形掩蔽特征，其有助于避免在MTJ膜叠层的蚀刻期间的副产物再沉积，从而提高工艺产率。 此外，侧壁间隔物特征可以在随后的处理步骤期间用作包封层，并且可以用作垂直接触以进行更高级别的金属化。

公开(公告)号：US06727589B2

公开(公告)日：2004-04-27

申请号：US09725862

申请日：2000-11-30

申请人： Stephen E. Greco ,  John P. Hummel ,  Joyce Liu ,  Vincent J. McGahay ,  Rebecca Mih ,  Kamalesh Srivastava

发明人： Stephen E. Greco ,  John P. Hummel ,  Joyce Liu ,  Vincent J. McGahay ,  Rebecca Mih ,  Kamalesh Srivastava

IPC分类号： H01L2348

CPC分类号： H01L21/76843 ,  H01L21/31116 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/7684

摘要： A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer may be either a single damascene or a dual damascene layer.

摘要翻译： 一种通过氧化FOX绝缘体的侧壁来保护半导体中的可流动的氧化物绝缘体的方法和结构，可选地将氧化的FOX侧壁氮化，然后覆盖包括侧壁在内的FOX绝缘体中的槽或多个槽的所有表面， 导电二级保护层。 在多层镶嵌结构中，FOX绝缘体的表面也被氧化，在其上沉积另外的氧化物层，并且沉积在氧化物层上的氮化物层。 然后重复步骤以获得可比较的镶嵌结构。 材料可以变化，并且每个镶嵌层可以是单镶嵌层或双镶嵌层。

公开(公告)号：US06593660B2

公开(公告)日：2003-07-15

申请号：US09866937

申请日：2001-05-29

申请人： Leena P. Buchwalter ,  Barbara Luther ,  Paul D. Agnello ,  John P. Hummel ,  Terence Lawrence Kane ,  Dirk Karl Manger ,  Paul Stephen McLaughlin ,  Anthony Kendall Stamper ,  Yun Yu Wang

发明人： Leena P. Buchwalter ,  Barbara Luther ,  Paul D. Agnello ,  John P. Hummel ,  Terence Lawrence Kane ,  Dirk Karl Manger ,  Paul Stephen McLaughlin ,  Anthony Kendall Stamper ,  Yun Yu Wang

IPC分类号： H01L2348

CPC分类号： H01L21/3185 ,  H01L21/0445 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76834

摘要： The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure. Interconnect structure including a material layer of Cu, Si and O, as essential elements, is formed between said copper wire or via and the inorganic barrier film.

摘要翻译： 本发明利用还原等离子体处理步骤来增强后续沉积的无机阻挡膜对铜线的粘附，或通过存在于诸如双镶嵌结构的半导体互连结构中。 在所述铜线或通孔与无机阻挡膜之间形成包括作为必需元素的Cu，Si和O的材料层的互连结构。

公开(公告)号：US06348736B1

公开(公告)日：2002-02-19

申请号：US09429257

申请日：1999-10-29

申请人： Vincent J. McGahay ,  John P. Hummel ,  Joyce Liu ,  Rebecca Mih ,  Kamalesh Srivastava ,  Robert Cook ,  Stephen E. Greco

发明人： Vincent J. McGahay ,  John P. Hummel ,  Joyce Liu ,  Rebecca Mih ,  Kamalesh Srivastava ,  Robert Cook ,  Stephen E. Greco

IPC分类号： H01L2348

CPC分类号： H01L21/76831 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/31144 ,  H01L21/3122 ,  H01L21/3124 ,  H01L21/76807

摘要： Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. A first protective layer is formed in situ on the dielectric material, such as by exposing the material to an oxygen-containing or flourine containing plasma. Also, by performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. The first protective layer and the surface protective covering can be formed by essentially identical processes. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.

摘要翻译： 抗蚀剂显影剂可以攻击一些先进的介电材料，例如可以用作集成电路芯片的表面和形成在介电材料表面上的布线层之间的绝缘体的倍半硅氧烷材料。 在电介质材料上原位形成第一保护层，例如通过将材料暴露于含氧或含氟的等离子体中。 此外，通过进行抗蚀剂剥离或蚀刻工艺，其中将反应物材料从电介质材料外部供应或从电介质材料释放出来，可以形成非常薄的中间材料的表面保护覆盖层，其不能抵抗显影剂或多个 可能损坏可流动的氧化物材料的其他材料。 第一保护层和表面保护层可以通过基本相同的方法形成。 因此，与芯片形成牢固的连接和通孔的双镶嵌工艺可以与具有特别低介电常数的先进电介质相兼容，以最小化导体电容并支持快速的信号传播和抗噪声性，即使导体彼此间隔紧密。

公开(公告)号：US07608538B2

公开(公告)日：2009-10-27

申请号：US11620497

申请日：2007-01-05

申请人： Hariklia Deligianni ,  Qiang Huang ,  John P. Hummel ,  Lubomyr T. Romankiw ,  Mary B. Rothwell

发明人： Hariklia Deligianni ,  Qiang Huang ,  John P. Hummel ,  Lubomyr T. Romankiw ,  Mary B. Rothwell

IPC分类号： H01L21/44

CPC分类号： H01L21/76879 ,  H01L21/2885 ,  Y10S205/925

摘要： The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete metal contact pad located on the substrate surface, an inter-level dielectric (ILD) layer over both the discrete metal contact pad and the substrate, and a metal via structure extending through the ILD layer onto the discrete metal contact pad. Next, a vertical via is formed in the template structure, which extends through the ILD layer onto the discrete metal contact pad. A vertical conductive structure is then formed in the vertical via by electroplating, which is conducted by applying an electroplating current to the discrete metal contact pad through the metal via structure. Preferably, the template structure comprises multiple discrete metal contact pads, multiple metal via structures, and multiple vertical vias for formation of multiple vertical conductive structures.

摘要翻译： 本发明涉及通过电镀形成垂直导电结构的方法。 具体地，首先形成模板结构，其包括衬底，位于衬底表面上的离散金属接触焊盘，分立金属接触焊盘和衬底两者之间的级间电介质（ILD）层，以及金属通孔结构 延伸穿过ILD层到分立的金属接触垫上。 接下来，在模板结构中形成垂直通孔，其延伸穿过ILD层到分立的金属接触垫上。 然后通过电镀在垂直通孔中形成垂直导电结构，电镀通过通过金属通孔结构将电镀电流施加到离散的金属接触焊盘来进行。 优选地，模板结构包括多个分立的金属接触焊盘，多个金属通孔结构以及用于形成多个垂直导电结构的多个垂直通孔。

公开(公告)号：US07531367B2

公开(公告)日：2009-05-12

申请号：US11333997

申请日：2006-01-18

申请人： Solomon Assefa ,  Michael C. Gaidis ,  Sivananda Kanakasabapathy ,  John P. Hummel ,  David W. Abraham

发明人： Solomon Assefa ,  Michael C. Gaidis ,  Sivananda Kanakasabapathy ,  John P. Hummel ,  David W. Abraham

IPC分类号： H01L21/00

CPC分类号： H01L43/12 ,  H01L27/222

摘要： Novel methods for reliably and reproducibly forming magnetic tunnel junctions in integrated circuits are described. In accordance with aspects of the invention, sidewall spacer features are utilized during the processing of the film stack. Advantageously, these sidewall spacer features create a tapered masking feature which helps to avoid byproduct redeposition during the etching of the MTJ film stack, thereby improving process yield. Moreover, the sidewall spacer features may be used as encapsulating layers during subsequent processing steps and as vertical contacts to higher levels of metallization.

摘要翻译： 描述了在集成电路中可靠且可重复地形成磁隧道结的新方法。 根据本发明的方面，在膜叠层的处理期间利用侧壁间隔物特征。 有利地，这些侧壁间隔物特征产生锥形掩蔽特征，其有助于避免在MTJ膜叠层的蚀刻期间的副产物再沉积，从而提高工艺产率。 此外，侧壁间隔物特征可以在随后的处理步骤期间用作包封层，并且可以用作垂直接触以进行更高级别的金属化。

公开(公告)号：US20080166874A1

公开(公告)日：2008-07-10

申请号：US11620497

申请日：2007-01-05

申请人： Hariklia Deligianni ,  Qiang Huang ,  John P. Hummel ,  Lubomyr T. Romankiw ,  Mary B. Rothwell

发明人： Hariklia Deligianni ,  Qiang Huang ,  John P. Hummel ,  Lubomyr T. Romankiw ,  Mary B. Rothwell

IPC分类号： H01L21/44

CPC分类号： H01L21/76879 ,  H01L21/2885 ,  Y10S205/925

摘要： The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete metal contact pad located on the substrate surface, an inter-level dielectric (ILD) layer over both the discrete metal contact pad and the substrate, and a metal via structure extending through the ILD layer onto the discrete metal contact pad. Next, a vertical via is formed in the template structure, which extends through the ILD layer onto the discrete metal contact pad. A vertical conductive structure is then formed in the vertical via by electroplating, which is conducted by applying an electroplating current to the discrete metal contact pad through the metal via structure. Preferably, the template structure comprises multiple discrete metal contact pads, multiple metal via structures, and multiple vertical vias for formation of multiple vertical conductive structures.

摘要翻译： 本发明涉及通过电镀形成垂直导电结构的方法。 具体地，首先形成模板结构，其包括衬底，位于衬底表面上的离散金属接触焊盘，分立金属接触焊盘和衬底两者之间的级间电介质（ILD）层，以及金属通孔结构 延伸穿过ILD层到分立的金属接触垫上。 接下来，在模板结构中形成垂直通孔，其延伸穿过ILD层到分立的金属接触垫上。 然后通过电镀在垂直通孔中形成垂直导电结构，电镀通过通过金属通孔结构将电镀电流施加到离散的金属接触焊盘来进行。 优选地，模板结构包括多个分立的金属接触焊盘，多个金属通孔结构以及用于形成多个垂直导电结构的多个垂直通孔。

公开(公告)号：US20080164617A1

公开(公告)日：2008-07-10

申请号：US11619623

申请日：2007-01-04

申请人： Solomon Assefa ,  Michael C. Gaidis ,  John P. Hummel ,  Sivananda K. Kanakasabapathy

发明人： Solomon Assefa ,  Michael C. Gaidis ,  John P. Hummel ,  Sivananda K. Kanakasabapathy

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L43/12 ,  H01L21/76807 ,  H01L21/76816

摘要： A method of forming vertical contacts in an integrated circuit that couple one or more metal lines in a given metallization level to first and second features occupying different levels in the integrated circuit comprises various processing steps. A first etch stop layer is formed overlying at least of portion of the first feature while a second etch stop layer is formed overlying at least a portion of the second feature. An ILD layer is formed overlying the first and second etch stop layers. A photolithographic mask is formed overlying the ILD layer. The photolithographic mask defines a first opening over the first feature and a second opening over the second feature. A first etch process etches a first hole in the ILD layer through the first opening in the photolithographic mask that lands on the first etch stop layer and etches a second hole in the ILD layer through the second opening that lands on the second etch stop layer. Subsequently, a second etch process further etches the first hole so that it lands on the first feature.

摘要翻译： 在集成电路中形成垂直触点的方法，其将给定金属化水平中的一个或多个金属线耦合到在集成电路中占据不同电平的第一和第二特征包括各种处理步骤。 形成第一蚀刻停止层，覆盖第一特征的至少一部分，而形成第二蚀刻停止层，覆盖第二特征的至少一部分。 形成覆盖在第一和第二蚀刻停止层上的ILD层。 在ILD层上形成光刻掩模。 光刻掩模限定第一特征上的第一开口和第二特征上的第二开口。 第一蚀刻工艺通过位于第一蚀刻停止层上的光刻掩模中的第一开口蚀刻ILD层中的第一孔，并通过第二开口蚀刻ILD层中的第二孔，该第二孔位于第二蚀刻停止层上。 随后，第二蚀刻工艺进一步蚀刻第一孔使其落在第一特征上。