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    Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same
    2.
    发明授权
    Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same 失效
    具有低介电常数绝缘体的芯片互连布线结构及其制造方法

    公开(公告)号：US06184121B2

    公开(公告)日：2001-02-06

    申请号：US09112919

    申请日：1998-07-09

    申请人： Leena P. Buchwalter ,  Alessandro Cesare Callegari ,  Stephan Alan Cohen ,  Teresita Ordonez Graham ,  John P. Hummel ,  Christopher V. Jahnes ,  Sampath Purushothaman ,  Katherine Lynn Saenger ,  Jane Margaret Shaw

    发明人： Leena P. Buchwalter ,  Alessandro Cesare Callegari ,  Stephan Alan Cohen ,  Teresita Ordonez Graham ,  John P. Hummel ,  Christopher V. Jahnes ,  Sampath Purushothaman ,  Katherine Lynn Saenger ,  Jane Margaret Shaw

    IPC分类号： H01L214763

    CPC分类号： H01L23/53228 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method to achieve a very low effective dielectric constant in high performance back end of the line chip interconnect wiring and the resulting multilayer structure are disclosed. The process involves fabricating the multilayer interconnect wiring structure by methods and materials currently known in the state of the art of semiconductor processing; removing the intralevel dielectric between the adjacent metal features by a suitable etching process; applying a thin passivation coating over the exposed etched structure; annealing the etched structure to remove plasma damage; laminating an insulating cover layer to the top surface of the passivated metal features; optionally depositing an insulating environmental barrier layer on top of the cover layer; etching vias in the environmental barrier layer, cover layer and the thin passivation layer for terminal pad contacts; and completing the device by fabricating terminal input/output pads. The method obviates issues such as processability and thermal stability associated with low dielectric constant materials by avoiding their use. Since air, which has the lowest dielectric constant, is used as the intralevel dielectric the structure created by this method would possess a very low capacitance and hence fast propagation speeds. Such structure is ideally suitable for high density interconnects required in high performance microelectronic device chips.

    摘要翻译： 公开了一种在线芯片互连布线和所得多层结构的高性能后端中实现非常低的有效介电常数的方法。 该方法涉及通过目前在半导体处理领域中已知的方法和材料制造多层互连布线结构; 通过合适的蚀刻工艺去除相邻金属特征之间的层间电介质; 在暴露的蚀刻结构上施加薄的钝化涂层; 退火蚀刻结构以去除等离子体损伤; 将绝缘覆盖层层压到钝化金属特征的顶表面; 可选地在覆盖层的顶部上沉积绝缘环境阻挡层; 在环境阻挡层，覆盖层和用于端子焊盘触点的薄钝化层中蚀刻通孔; 并通过制造端子输入/输出焊盘来完成该器件。 该方法通过避免其使用而消除了与低介电常数材料相关的加工性和热稳定性等问题。 由于具有最低介电常数的空气被用作体内电介质，所以通过该方法产生的结构将具有非常低的电容并因此具有快速的传播速度。 这种结构理想地适用于高性能微电子器件芯片所需的高密度互连。

    Magnetic switching device
    6.
    发明授权
    Magnetic switching device 失效
    磁性开关装置

    公开(公告)号：US07097777B2

    公开(公告)日：2006-08-29

    申请号：US11070856

    申请日：2005-03-02

    申请人： Gregory Costrini ,  John P. Hummel ,  George Stojakovic ,  Kia-Seng Low

    发明人： Gregory Costrini ,  John P. Hummel ,  George Stojakovic ,  Kia-Seng Low

    IPC分类号： B44C1/22

    CPC分类号： G11C11/16 ,  B82Y25/00 ,  B82Y40/00 ,  H01F41/308 ,  H01L43/12

    摘要： A method of forming a magnetic switching device is provided. The method includes depositing a bilayer hardmask, which may comprise a first mask layer of titanium nitride with a second mask layer of tungsten formed thereon. A first lithography process is performed to pattern the second mask layer, and a second lithography process is performed to pattern the first mask layer. Thereafter, the magnetic tunnel junction stack may be patterned in accordance with the first mask layer. An etching process may be performed to further pattern the first mask layer in accordance with the second mask layer. An optional passivation layer may be formed over the first mask layer and the second mask layer.

    摘要翻译： 提供一种形成磁性开关装置的方法。 该方法包括沉积双层硬掩模，其可以包括氮化钛的第一掩模层和形成在其上的钨的第二掩模层。 执行第一光刻处理以对第二掩模层进行图案化，并且执行第二光刻处理以对第一掩模层进行图案化。 此后，根据第一掩模层可以对磁性隧道结堆叠进行构图。 可以执行蚀刻工艺以根据第二掩模层进一步图案化第一掩模层。 可以在第一掩模层和第二掩模层上形成可选的钝化层。

    Post metalization chem-mech polishing dielectric etch
    8.
    发明授权
    Post metalization chem-mech polishing dielectric etch 失效
    后金属化化学抛光电介质蚀刻

    公开(公告)号：US06551924B1

    公开(公告)日：2003-04-22

    申请号：US09432683

    申请日：1999-11-02

    申请人： Timothy J. Dalton ,  John P. Hummel

    发明人： Timothy J. Dalton ,  John P. Hummel

    IPC分类号： H01L214763

    CPC分类号： H01L21/76802 ,  H01L21/76807 ,  H01L21/76885

    摘要： A method for etching an insulating layer without damage to the conducting layer and associated liner layer within the insulating layer. A dielectric layer is deposited on a semiconductor substrate and then patterned. A liner layer and a conducting layer are then deposited within the patterned dielectric. A passivating layer is deposited on top of the conducting layer after the conducting layer has been planarized through chemical-mechanical polishing while simultaneously etching the dielectric layer through a process that does not damage the underlying conducting and liner layers. The insulating layer is preferably a dielectric such as silicon dioxide and the liner layer is tantalum, tantalum nitride or a combination of the two. The passivating layer preferably consists of carbon and fluorine bound up in various chemical forms. The conducting layer preferably consists of copper. Recipes for simultaneously forming the passivating layer and etching the dielectric layer, and for removing the passivating layer without damaging the underlying conducting and liner layers are provided.

    摘要翻译： 一种用于蚀刻绝缘层而不损坏绝缘层内的导电层和相关衬里层的方法。 介电层沉积在半导体衬底上，然后构图。 然后在图案化的电介质中沉积衬垫层和导电层。 在通过化学机械抛光平面化导电层之后，在导电层的顶部上沉积钝化层，同时通过不损坏下面的导电层和衬层的工艺同时蚀刻介电层。 绝缘层优选是诸如二氧化硅的电介质，并且衬垫层是钽，氮化钽或两者的组合。 钝化层优选由以各种化学形式结合的碳和氟组成。 导电层优选由铜组成。 提供了用于同时形成钝化层和蚀刻介电层以及用于去除钝化层而不损坏下面的导电层和衬层的配方。

    Formation of vertical devices by electroplating
    9.
    发明授权
    Formation of vertical devices by electroplating 有权
    通过电镀形成垂直装置

    公开(公告)号：US08247905B2

    公开(公告)日：2012-08-21

    申请号：US12538782

    申请日：2009-08-10

    申请人： Hariklia Deligianni ,  Qiang Huang ,  John P. Hummel ,  Lubomyr T. Romankiw ,  Mary B. Rothwell

    发明人： Hariklia Deligianni ,  Qiang Huang ,  John P. Hummel ,  Lubomyr T. Romankiw ,  Mary B. Rothwell

    IPC分类号： H01L29/40

    CPC分类号： H01L21/76879 ,  H01L21/2885 ,  Y10S205/925

    摘要： The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete metal contact pad located on the substrate surface, an inter-level dielectric (ILD) layer over both the discrete metal contact pad and the substrate, and a metal via structure extending through the ILD layer onto the discrete metal contact pad. Next, a vertical via is formed in the template structure, which extends through the ILD layer onto the discrete metal contact pad. A vertical conductive structure is then formed in the vertical via by electroplating, which is conducted by applying an electroplating current to the discrete metal contact pad through the metal via structure. Preferably, the template structure comprises multiple discrete metal contact pads, multiple metal via structures, and multiple vertical vias for formation of multiple vertical conductive structures.

    摘要翻译： 本发明涉及通过电镀形成垂直导电结构的方法。 具体地，首先形成模板结构，其包括衬底，位于衬底表面上的离散金属接触焊盘，分立金属接触焊盘和衬底两者之间的级间电介质（ILD）层，以及金属通孔结构 延伸穿过ILD层到分立的金属接触垫上。 接下来，在模板结构中形成垂直通孔，其延伸穿过ILD层到分立的金属接触垫上。 然后通过电镀在垂直通孔中形成垂直导电结构，电镀通过通过金属通孔结构将电镀电流施加到离散的金属接触焊盘来进行。 优选地，模板结构包括多个分立的金属接触焊盘，多个金属通孔结构以及用于形成多个垂直导电结构的多个垂直通孔。

    Method of forming vertical contacts in integrated circuits
    10.
    发明授权
    Method of forming vertical contacts in integrated circuits 有权
    在集成电路中形成垂直触点的方法

    公开(公告)号：US07803639B2

    公开(公告)日：2010-09-28

    申请号：US11619623

    申请日：2007-01-04

    申请人： Solomon Assefa ,  Michael C. Gaidis ,  John P. Hummel ,  Sivananda K. Kanakasabapathy

    发明人： Solomon Assefa ,  Michael C. Gaidis ,  John P. Hummel ,  Sivananda K. Kanakasabapathy

    IPC分类号： H01L21/00 ,  H01L21/4763 ,  H01L21/44

    CPC分类号： H01L43/12 ,  H01L21/76807 ,  H01L21/76816

    摘要： A method of forming vertical contacts in an integrated circuit that couple one or more metal lines in a given metallization level to first and second features occupying different levels in the integrated circuit comprises various processing steps. A first etch stop layer is formed overlying at least of portion of the first feature while a second etch stop layer is formed overlying at least a portion of the second feature. An ILD layer is formed overlying the first and second etch stop layers. A photolithographic mask is formed overlying the ILD layer. The photolithographic mask defines a first opening over the first feature and a second opening over the second feature. A first etch process etches a first hole in the ILD layer through the first opening in the photolithographic mask that lands on the first etch stop layer and etches a second hole in the ILD layer through the second opening that lands on the second etch stop layer. Subsequently, a second etch process further etches the first hole so that it lands on the first feature.

    摘要翻译： 在集成电路中形成垂直触点的方法，其将给定金属化水平中的一个或多个金属线耦合到在集成电路中占据不同电平的第一和第二特征包括各种处理步骤。 形成第一蚀刻停止层，覆盖第一特征的至少一部分，而形成第二蚀刻停止层，覆盖第二特征的至少一部分。 形成覆盖在第一和第二蚀刻停止层上的ILD层。 在ILD层上形成光刻掩模。 光刻掩模限定第一特征上的第一开口和第二特征上的第二开口。 第一蚀刻工艺通过位于第一蚀刻停止层上的光刻掩模中的第一开口蚀刻ILD层中的第一孔，并通过第二开口蚀刻ILD层中的第二孔，该第二孔位于第二蚀刻停止层上。 随后，第二蚀刻工艺进一步蚀刻第一孔使其落在第一特征上。