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12 条记录 (耗时 0.039 秒)

    Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same
    2.
    发明授权
    Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same 失效
    具有低介电常数绝缘体的芯片互连布线结构及其制造方法

    公开(公告)号：US06184121B2

    公开(公告)日：2001-02-06

    申请号：US09112919

    申请日：1998-07-09

    申请人： Leena P. Buchwalter ,  Alessandro Cesare Callegari ,  Stephan Alan Cohen ,  Teresita Ordonez Graham ,  John P. Hummel ,  Christopher V. Jahnes ,  Sampath Purushothaman ,  Katherine Lynn Saenger ,  Jane Margaret Shaw

    发明人： Leena P. Buchwalter ,  Alessandro Cesare Callegari ,  Stephan Alan Cohen ,  Teresita Ordonez Graham ,  John P. Hummel ,  Christopher V. Jahnes ,  Sampath Purushothaman ,  Katherine Lynn Saenger ,  Jane Margaret Shaw

    IPC分类号： H01L214763

    CPC分类号： H01L23/53228 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method to achieve a very low effective dielectric constant in high performance back end of the line chip interconnect wiring and the resulting multilayer structure are disclosed. The process involves fabricating the multilayer interconnect wiring structure by methods and materials currently known in the state of the art of semiconductor processing; removing the intralevel dielectric between the adjacent metal features by a suitable etching process; applying a thin passivation coating over the exposed etched structure; annealing the etched structure to remove plasma damage; laminating an insulating cover layer to the top surface of the passivated metal features; optionally depositing an insulating environmental barrier layer on top of the cover layer; etching vias in the environmental barrier layer, cover layer and the thin passivation layer for terminal pad contacts; and completing the device by fabricating terminal input/output pads. The method obviates issues such as processability and thermal stability associated with low dielectric constant materials by avoiding their use. Since air, which has the lowest dielectric constant, is used as the intralevel dielectric the structure created by this method would possess a very low capacitance and hence fast propagation speeds. Such structure is ideally suitable for high density interconnects required in high performance microelectronic device chips.

    摘要翻译： 公开了一种在线芯片互连布线和所得多层结构的高性能后端中实现非常低的有效介电常数的方法。 该方法涉及通过目前在半导体处理领域中已知的方法和材料制造多层互连布线结构; 通过合适的蚀刻工艺去除相邻金属特征之间的层间电介质; 在暴露的蚀刻结构上施加薄的钝化涂层; 退火蚀刻结构以去除等离子体损伤; 将绝缘覆盖层层压到钝化金属特征的顶表面; 可选地在覆盖层的顶部上沉积绝缘环境阻挡层; 在环境阻挡层，覆盖层和用于端子焊盘触点的薄钝化层中蚀刻通孔; 并通过制造端子输入/输出焊盘来完成该器件。 该方法通过避免其使用而消除了与低介电常数材料相关的加工性和热稳定性等问题。 由于具有最低介电常数的空气被用作体内电介质，所以通过该方法产生的结构将具有非常低的电容并因此具有快速的传播速度。 这种结构理想地适用于高性能微电子器件芯片所需的高密度互连。

    Sputter deposition of hydrogenated amorphous carbon film and applications thereof
    5.
    发明授权
    Sputter deposition of hydrogenated amorphous carbon film and applications thereof 失效
    氢化无定形碳膜的溅射沉积及其应用

    公开(公告)号：US5830332A

    公开(公告)日：1998-11-03

    申请号：US781080

    申请日：1997-01-09

    申请人： Edward D. Babich ,  Alessandro Cesare Callegari ,  Fuad Elias Doany ,  Sampath Purushothaman

    发明人： Edward D. Babich ,  Alessandro Cesare Callegari ,  Fuad Elias Doany ,  Sampath Purushothaman

    IPC分类号： C23C14/06 ,  C23C14/34 ,  G02B1/10 ,  G03F1/00 ,  G03F1/26 ,  G03F1/32 ,  G03F1/34 ,  H01L21/205

    CPC分类号： G03F1/32 ,  C23C14/0605 ,  G03F1/26 ,  G03F1/34

    摘要： The present invention relates to a method of reactive sputtering for depositing an amorphous hydrogenated carbon film (a-C:H) from an argon/hydrocarbon/hydrogen/oxygen plasma, preferably an Ar/acetylene-helium/hydrogen/oxygen plasma. Such films are optically transparent in the visible range and partially absorbing at ultraviolet (UV) and deep UV (DUV) wavelengths, in particular, 365, and 248, 193 nm. Moreover, the films produced by the present invention are amorphous, hard, scratch resistant, and etchable by excimer laser ablation or by oxygen reactive ion etch process. Because of these unique properties, these films can be used to form a patterned absorber for UV and DUV single layer attenuated phase shift masks. Film absorption can also be increased such that these films can be used to fabricate conventional photolithographic shadow masks.

    摘要翻译： 本发明涉及一种用于从氩/烃/氢/氧等离子体，优选Ar /乙炔 - 氦/氢/氧等离子体沉积无定形氢化碳膜（a-C：H）的反应溅射方法。 这种膜在可见光范围内是光学透明的，并且在紫外（UV）和深紫外（DUV）波长，特别是365和248,193nm处部分吸收。 此外，本发明生产的薄膜是非晶的，硬的，耐划伤的，并且可以通过准分子激光烧蚀或通过氧反应离子蚀刻工艺进行蚀刻。 由于这些独特的性质，这些膜可用于形成用于UV和DUV单层衰减相移掩模的图案化吸收体。 也可以增加膜吸收，使得这些膜可用于制造常规光刻阴影掩模。

    Low temperature thin film transistor fabrication
    6.
    发明授权
    Low temperature thin film transistor fabrication 有权
    低温薄膜晶体管制造

    公开(公告)号：US06207472B1

    公开(公告)日：2001-03-27

    申请号：US09265161

    申请日：1999-03-09

    申请人： Alessandro Cesare Callegari ,  Christos Dimitrios Dimitrakopoulos ,  Sampath Purushothaman

    发明人： Alessandro Cesare Callegari ,  Christos Dimitrios Dimitrakopoulos ,  Sampath Purushothaman

    IPC分类号： H01L5140

    CPC分类号： H01L51/0545 ,  H01L21/31691 ,  H01L51/0052

    摘要： The invention broadens the range of materials and processes that are available for Thin Film Transistor (TFT) devices by providing in the device structure an organic semiconductor layer that is in contact with an inorganic mixed oxide gate insulator involving room temperature processing at up to 150 degrees C. A TFT of the invention has a pentacene semiconductor layer in contact with a barium zirconate titanate gate oxide layer formed on a polycarbonate transparent substrate employing at least one of the techniques of sputtering, evaporation and laser ablation.

    摘要翻译： 本发明通过在器件结构中提供与无机混合氧化物栅极绝缘体接触的有机半导体层来扩展可用于薄膜晶体管（TFT）器件的材料和工艺的范围，所述有机半导体层涉及在高达150度的室温处理 本发明的CA TFT具有与使用溅射，蒸发和激光烧蚀技术中的至少一种技术形成在聚碳酸酯透明基板上的锆酸锆酸盐栅极氧化物层接触的并五苯半导体层。

    Reactive sputtering method for forming metal-silicon layer
    10.
    发明授权
    Reactive sputtering method for forming metal-silicon layer 有权
    用于形成金属硅层的反应溅射方法

    公开(公告)号：US06413386B1

    公开(公告)日：2002-07-02

    申请号：US09619512

    申请日：2000-07-19

    申请人： Alessandro Cesare Callegari ,  Eduard Albert Cartier ,  Michael Abramovich Gribelyuk ,  Harald Franz Okorn-Schmidt ,  Theodore Harold Zabel

    发明人： Alessandro Cesare Callegari ,  Eduard Albert Cartier ,  Michael Abramovich Gribelyuk ,  Harald Franz Okorn-Schmidt ,  Theodore Harold Zabel

    IPC分类号： C23C1434

    CPC分类号： C23C14/08 ,  C23C14/0057

    摘要： Within a method for forming a metal-silicon layer there is first provided a reactor chamber. There is then positioned within the reactor chamber a substrate spaced from a metal source target. There is also provided within the reactor chamber a minimum of a sputter material and a reactive silicon material. There is then sputtered the metal source target positioned within the reactor chamber with the sputter material provided within the reactor chamber in the presence of the reactive silicon material provided within the reactor chamber to form a metal-silicon layer over the substrate. The method is particularly useful for forming metal silicate layers, metal silicon nitride layers and metal silicon oxynitride layers within microelectronic fabrications. An alternative method employs: (1) a silicon source target rather than a metal source target; and (2) a reactive metal material rather than a reactive silicon material.

    摘要翻译： 在形成金属硅层的方法中，首先提供反应室。 然后在反应器室内定位与金属源靶间隔开的衬底。 在反应器室内还设置有最少的溅射材料和反应性硅材料。 然后在设置在反应器室内的反应性硅材料的存在下，将设置在反应器室内的溅射材料溅射到位于反应器室内的金属源靶，以在衬底上形成金属硅层。 该方法对于在微电子制造中形成金属硅酸盐层，金属氮化硅层和金属氮氧化硅层是特别有用的。 替代方法采用：（1）硅源靶而不是金属源靶; 和（2）反应性金属材料而不是反应性硅材料。