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US06893948B2 Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size 失效
通过沉积不同晶粒尺寸的多晶硅来减少多晶硅栅电极中的多晶硅耗尽的方法

Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size
Abstract:
Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.
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