Invention Grant
US06893948B2 Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size
失效
通过沉积不同晶粒尺寸的多晶硅来减少多晶硅栅电极中的多晶硅耗尽的方法
- Patent Title: Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size
- Patent Title (中): 通过沉积不同晶粒尺寸的多晶硅来减少多晶硅栅电极中的多晶硅耗尽的方法
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Application No.: US10616962Application Date: 2003-07-11
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Publication No.: US06893948B2Publication Date: 2005-05-17
- Inventor: Arne W. Ballantine , Kevin K. Chan , Jeffrey D. Gilbert , Kevin M. Houlihan , Glen L. Miles , James J. Quinlivan , Samuel C. Ramac , Michael B. Rice , Beth A. Ward
- Applicant: Arne W. Ballantine , Kevin K. Chan , Jeffrey D. Gilbert , Kevin M. Houlihan , Glen L. Miles , James J. Quinlivan , Samuel C. Ramac , Michael B. Rice , Beth A. Ward
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Connolly Bove Lodge & Hutz LLP
- Agent Larry J. Hume; William D. Sabo
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L21/336 ; H01L29/49 ; H01L21/20 ; H01L21/3205 ; H01L21/4763

Abstract:
Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.
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