公开(公告)号：US07291568B2

公开(公告)日：2007-11-06

申请号：US10604905

申请日：2003-08-26

Applicant: Jay S. Burnham ,  James S. Nakos ,  James J. Quinlivan ,  Bernie A. Roque, Jr. ,  Steven M. Shank ,  Beth A. Ward

Inventor： Jay S. Burnham ,  James S. Nakos ,  James J. Quinlivan ,  Bernie A. Roque, Jr. ,  Steven M. Shank ,  Beth A. Ward

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/28202 ,  H01L21/28035 ,  H01L21/3144 ,  H01L29/518

Abstract: A method of fabricating a gate dielectric layer, including: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; performing a plasma nitridation in a reducing atmosphere to convert the silicon dioxide layer into a silicon oxynitride layer. The dielectric layer so formed may be used in the fabrication of MOSFETs.

Abstract translation: 一种制造栅极电介质层的方法，包括：提供衬底; 在所述基板的顶表面上形成二氧化硅层; 在还原气氛中进行等离子体氮化，将二氧化硅层转换成氮氧化硅层。 如此形成的电介质层可用于制造MOSFET。

公开(公告)号：US07109559B2

公开(公告)日：2006-09-19

申请号：US10982999

申请日：2004-11-05

Applicant: Mukesh V. Khare ,  Christopher P. D'Emic ,  Thomas T. Hwang ,  Paul C. Jamison ,  James J. Quinlivan ,  Beth A. Ward

Inventor： Mukesh V. Khare ,  Christopher P. D'Emic ,  Thomas T. Hwang ,  Paul C. Jamison ,  James J. Quinlivan ,  Beth A. Ward

IPC: H01L29/76 ,  H01L29/94

CPC classification number: H01L29/518 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/3144

Abstract: A method for forming a gate dielectric for an integrated circuit device. In an exemplary embodiment of the invention, the method includes forming an initial oxynitride layer upon a substrate material, the oxynitride layer having an initial physical thickness. The initial oxynitride layer is then subjected to a plasma nitridation, the plasma nitridation resulting in final oxynitride layer having a final physical thickness.

Abstract translation: 一种用于形成用于集成电路器件的栅极电介质的方法。 在本发明的示例性实施例中，该方法包括在基底材料上形成初始氧氮化物层，该氮氧化物层具有初始物理厚度。 然后对初始氧氮化物层进行等离子体氮化处理，等离子体氮化导致最终的氧氮化物层具有最终的物理厚度。

公开(公告)号：US06893948B2

公开(公告)日：2005-05-17

申请号：US10616962

申请日：2003-07-11

Applicant: Arne W. Ballantine ,  Kevin K. Chan ,  Jeffrey D. Gilbert ,  Kevin M. Houlihan ,  Glen L. Miles ,  James J. Quinlivan ,  Samuel C. Ramac ,  Michael B. Rice ,  Beth A. Ward

Inventor： Arne W. Ballantine ,  Kevin K. Chan ,  Jeffrey D. Gilbert ,  Kevin M. Houlihan ,  Glen L. Miles ,  James J. Quinlivan ,  Samuel C. Ramac ,  Michael B. Rice ,  Beth A. Ward

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L21/20 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/28035 ,  H01L29/4925 ,  H01L29/665

Abstract: Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.

Abstract translation: 通过在受控条件下沉积多晶硅来减少多晶硅栅电极中的多晶硅电耗，从而通过多晶硅的厚度来改变晶粒尺寸。 所得到的结构可以具有两个或更多个相应晶粒尺寸的深度连续的区域，并且晶粒尺寸的选择被引导以最大限度地使栅极电介质附近的多晶硅中的掺杂剂活化最大化，并且将多晶硅的电阻定制在第一 区域并且远离栅极电介质。 该方法和所得结构有利地用于形成FET和掺杂多晶硅电阻器。

公开(公告)号：US06893979B2

公开(公告)日：2005-05-17

申请号：US09809663

申请日：2001-03-15

Applicant: Mukesh V. Khare ,  Christopher P. D'Emic ,  Thomas T. Hwang ,  Paul C. Jamison ,  James J. Quinlivan ,  Beth A. Ward

Inventor： Mukesh V. Khare ,  Christopher P. D'Emic ,  Thomas T. Hwang ,  Paul C. Jamison ,  James J. Quinlivan ,  Beth A. Ward

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/314 ,  H01L21/318 ,  H01L29/51 ,  H01L29/78 ,  H01L21/31 ,  H01L21/469

CPC classification number: H01L29/518 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/3144

Abstract: A method for forming a gate dielectric for an integrated circuit device. In an exemplary embodiment of the invention, the method includes forming an initial oxynitride layer upon a substrate material, the oxynitride layer having an initial physical thickness. The initial oxynitride layer is then subjected to a plasma nitridation, the plasma nitridation resulting in final oxynitride layer having a final physical thickness.

Abstract translation: 一种用于形成用于集成电路器件的栅极电介质的方法。 在本发明的示例性实施例中，该方法包括在基底材料上形成初始氧氮化物层，该氮氧化物层具有初始物理厚度。 然后对初始氧氮化物层进行等离子体氮化处理，等离子体氮化导致最终的氧氮化物层具有最终的物理厚度。

公开(公告)号：US06670263B2

公开(公告)日：2003-12-30

申请号：US09802702

申请日：2001-03-10

Applicant: Arne W. Ballantine ,  Kevin K. Chan ,  Jeffrey D. Gilbert ,  Kevin M. Houlihan ,  Glen L. Miles ,  James J. Quinlivan ,  Samuel C. Ramac ,  Michael B. Rice ,  Beth A. Ward

Inventor： Arne W. Ballantine ,  Kevin K. Chan ,  Jeffrey D. Gilbert ,  Kevin M. Houlihan ,  Glen L. Miles ,  James J. Quinlivan ,  Samuel C. Ramac ,  Michael B. Rice ,  Beth A. Ward

IPC: H01L213205

CPC classification number: H01L21/28035 ,  H01L29/4925 ,  H01L29/665

Abstract: Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.

公开(公告)号：US06909157B2

公开(公告)日：2005-06-21

申请号：US10652307

申请日：2003-09-02

Applicant: Jay S. Burnham ,  James S. Nakos ,  James J. Quinlivan ,  Steven M. Shank ,  Deborah A. Tucker ,  Beth A. Ward

Inventor： Jay S. Burnham ,  James S. Nakos ,  James J. Quinlivan ,  Steven M. Shank ,  Deborah A. Tucker ,  Beth A. Ward

IPC: H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L29/51 ,  H01L29/76

CPC classification number: H01L21/28202 ,  H01L21/28185 ,  H01L21/28211 ,  H01L21/3144 ,  H01L21/31612 ,  H01L21/3185 ,  H01L29/513 ,  H01L29/518

Abstract: Methods such as Remote Plasma Nitridation (RPN) are used to introduce nitrogen into a gate dielectric layer. However, these methods yield nitrided layers where the layers are not uniform, both in cross-sectional profile and in nitrogen profile. Subjecting the nitrided layer to an additional NO anneal process increases the uniformity of the nitrided layer.

公开(公告)号：US08709887B2

公开(公告)日：2014-04-29

申请号：US11778238

申请日：2007-07-16

Applicant: Jay S. Burnham ,  James S. Nakos ,  James J. Quinlivan ,  Bernie Roque, Jr. ,  Steven M. Shank ,  Beth A. Ward

Inventor： Jay S. Burnham ,  James S. Nakos ,  James J. Quinlivan ,  Bernie Roque, Jr. ,  Steven M. Shank ,  Beth A. Ward

IPC: H01L21/336

CPC classification number: H01L21/28202 ,  H01L21/28035 ,  H01L21/3144 ,  H01L29/518

Abstract: A method of fabricating a gate dielectric layer. The method includes: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; performing a plasma nitridation in a reducing atmosphere to convert the silicon dioxide layer into a silicon oxynitride layer. The dielectric layer so formed may be used in the fabrication of MOSFETs.

Abstract translation: 一种制造栅极电介质层的方法。 该方法包括：提供衬底; 在所述基板的顶表面上形成二氧化硅层; 在还原气氛中进行等离子体氮化，将二氧化硅层转换成氮氧化硅层。 如此形成的电介质层可用于制造MOSFET。

公开(公告)号：US07714366B2

公开(公告)日：2010-05-11

申请号：US10904565

申请日：2004-11-16

Applicant: Arne W. Ballantine ,  Kevin K. Chan ,  Jeffrey D. Gilbert ,  Kevin M. Houlihan ,  Glen L. Miles ,  James J. Quinlivan ,  Samuel C. Ramac ,  Michael B. Rice ,  Beth A. Ward

Inventor： Arne W. Ballantine ,  Kevin K. Chan ,  Jeffrey D. Gilbert ,  Kevin M. Houlihan ,  Glen L. Miles ,  James J. Quinlivan ,  Samuel C. Ramac ,  Michael B. Rice ,  Beth A. Ward

IPC: H01L27/088 ,  H01L29/78

CPC classification number: H01L21/28035 ,  H01L29/4925 ,  H01L29/665

Abstract: Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting CMOS transistor may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size may be directed to maximize dopant activation in the polysilicon near the gate dielectric and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. A region of polycrystalline silicon may have a varying grain size as a function of a distance measured from a surface of the dielectric film.

Abstract translation: 通过在受控条件下沉积多晶硅来减少多晶硅栅电极中的多晶硅电耗，从而通过多晶硅的厚度来改变晶粒尺寸。 所得到的CMOS晶体管可以具有各自的晶粒尺寸的两个或更多个深度连续的区域，并且可以针对晶体尺寸的选择来最大化在栅极电介质附近的多晶硅中的掺杂剂活化，并且将多晶硅的电阻调整到高于该 第一区域并且远离栅极电介质。 多晶硅的区域可以具有作为从电介质膜的表面测量的距离的函数的变化的晶粒尺寸。

公开(公告)号：US06706644B2

公开(公告)日：2004-03-16

申请号：US10206427

申请日：2002-07-26

Applicant: Jay S. Burnham ,  James S. Nakos ,  James J. Quinlivan ,  Steven M. Shank ,  Deborah A. Tucker ,  Beth A. Ward

Inventor： Jay S. Burnham ,  James S. Nakos ,  James J. Quinlivan ,  Steven M. Shank ,  Deborah A. Tucker ,  Beth A. Ward

IPC: H01L2131

CPC classification number: H01L21/28202 ,  H01L21/28185 ,  H01L21/28211 ,  H01L21/3144 ,  H01L21/31612 ,  H01L21/3185 ,  H01L29/513 ,  H01L29/518

Abstract: Methods such as Remote Plasma Nitridation (RPN) are used to introduce nitrogen into a gate dielectric layer. However, these methods yield nitrided layers where the layers are not uniform, both in cross-sectional profile and in nitrogen profile. Subjecting the nitrided layer to an additional NO anneal process increases the uniformity of the nitrided layer.

Abstract translation: 使用诸如远程等离子体氮化（RPN）的方法将氮气引入栅极介电层。 然而，这些方法产生氮化层，其中层的横截面轮廓和氮分布都不均匀。 使氮化层进行额外的NO退火工艺增加了氮化层的均匀性。