公开(公告)号：US07714366B2

公开(公告)日：2010-05-11

申请号：US10904565

申请日：2004-11-16

申请人： Arne W. Ballantine ,  Kevin K. Chan ,  Jeffrey D. Gilbert ,  Kevin M. Houlihan ,  Glen L. Miles ,  James J. Quinlivan ,  Samuel C. Ramac ,  Michael B. Rice ,  Beth A. Ward

发明人： Arne W. Ballantine ,  Kevin K. Chan ,  Jeffrey D. Gilbert ,  Kevin M. Houlihan ,  Glen L. Miles ,  James J. Quinlivan ,  Samuel C. Ramac ,  Michael B. Rice ,  Beth A. Ward

IPC分类号： H01L27/088 ,  H01L29/78

CPC分类号： H01L21/28035 ,  H01L29/4925 ,  H01L29/665

摘要： Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting CMOS transistor may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size may be directed to maximize dopant activation in the polysilicon near the gate dielectric and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. A region of polycrystalline silicon may have a varying grain size as a function of a distance measured from a surface of the dielectric film.

摘要翻译： 通过在受控条件下沉积多晶硅来减少多晶硅栅电极中的多晶硅电耗，从而通过多晶硅的厚度来改变晶粒尺寸。 所得到的CMOS晶体管可以具有各自的晶粒尺寸的两个或更多个深度连续的区域，并且可以针对晶体尺寸的选择来最大化在栅极电介质附近的多晶硅中的掺杂剂活化，并且将多晶硅的电阻调整到高于该 第一区域并且远离栅极电介质。 多晶硅的区域可以具有作为从电介质膜的表面测量的距离的函数的变化的晶粒尺寸。

公开(公告)号：US06893948B2

公开(公告)日：2005-05-17

申请号：US10616962

申请日：2003-07-11

申请人： Arne W. Ballantine ,  Kevin K. Chan ,  Jeffrey D. Gilbert ,  Kevin M. Houlihan ,  Glen L. Miles ,  James J. Quinlivan ,  Samuel C. Ramac ,  Michael B. Rice ,  Beth A. Ward

发明人： Arne W. Ballantine ,  Kevin K. Chan ,  Jeffrey D. Gilbert ,  Kevin M. Houlihan ,  Glen L. Miles ,  James J. Quinlivan ,  Samuel C. Ramac ,  Michael B. Rice ,  Beth A. Ward

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L21/20 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/28035 ,  H01L29/4925 ,  H01L29/665

摘要： Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.

摘要翻译： 通过在受控条件下沉积多晶硅来减少多晶硅栅电极中的多晶硅电耗，从而通过多晶硅的厚度来改变晶粒尺寸。 所得到的结构可以具有两个或更多个相应晶粒尺寸的深度连续的区域，并且晶粒尺寸的选择被引导以最大限度地使栅极电介质附近的多晶硅中的掺杂剂活化最大化，并且将多晶硅的电阻定制在第一 区域并且远离栅极电介质。 该方法和所得结构有利地用于形成FET和掺杂多晶硅电阻器。

公开(公告)号：US06670263B2

公开(公告)日：2003-12-30

申请号：US09802702

申请日：2001-03-10

申请人： Arne W. Ballantine ,  Kevin K. Chan ,  Jeffrey D. Gilbert ,  Kevin M. Houlihan ,  Glen L. Miles ,  James J. Quinlivan ,  Samuel C. Ramac ,  Michael B. Rice ,  Beth A. Ward

发明人： Arne W. Ballantine ,  Kevin K. Chan ,  Jeffrey D. Gilbert ,  Kevin M. Houlihan ,  Glen L. Miles ,  James J. Quinlivan ,  Samuel C. Ramac ,  Michael B. Rice ,  Beth A. Ward

IPC分类号： H01L213205

CPC分类号： H01L21/28035 ,  H01L29/4925 ,  H01L29/665

摘要： Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.

公开(公告)号：US06255200B1

公开(公告)日：2001-07-03

申请号：US09312943

申请日：1999-05-17

申请人： Arne W. Ballantine ,  Kevin K. Chan ,  Gary L. Langdeau ,  Michael B. Rice

发明人： Arne W. Ballantine ,  Kevin K. Chan ,  Gary L. Langdeau ,  Michael B. Rice

IPC分类号： H01L2136

CPC分类号： H01L21/28525 ,  C23C16/24 ,  Y10S148/122

摘要： A process for depositing polycrystalline silicon, including exposing a semiconductor substrate on which the polycrystalline silicon is to be deposited to a silicon containing gas and a temperature of about 680° C. to about 800° C.

摘要翻译： 一种用于沉积多晶硅的方法，包括将其上沉积多晶硅的半导体衬底暴露于含硅气体和约680℃至约800℃的温度。

公开(公告)号：US06444592B1

公开(公告)日：2002-09-03

申请号：US09597765

申请日：2000-06-20

申请人： Arne W. Ballantine ,  Douglas A. Buchanan ,  Eduard A. Cartier ,  Kevin K. Chan ,  Matthew W. Copel ,  Christopher P. D'Emic ,  Evgeni P. Gousev ,  Fenton Read McFeely ,  Joseph S. Newbury ,  Harald F. Okorn-Schmidt ,  Patrick R. Varekamp ,  Theodore H. Zabel

发明人： Arne W. Ballantine ,  Douglas A. Buchanan ,  Eduard A. Cartier ,  Kevin K. Chan ,  Matthew W. Copel ,  Christopher P. D'Emic ,  Evgeni P. Gousev ,  Fenton Read McFeely ,  Joseph S. Newbury ,  Harald F. Okorn-Schmidt ,  Patrick R. Varekamp ,  Theodore H. Zabel

IPC分类号： H01L21469

CPC分类号： H01L21/31691 ,  H01L28/56

摘要： A method for integrating a high-k material into CMOS processing schemes is provided. The method includes forming an interfacial oxide, oxynitride and/or nitride layer on a device region of a semiconductor substrate, said interfacial layer having a thickness of less than 10 Å; and (b) forming a high-k dielectric material on said interfacial oxide, oxynitride and/or, nitride layer, said high-k dielectric having a dielectric constant, k, of greater than 8.

摘要翻译： 提供了一种将高k材料集成到CMOS处理方案中的方法。 该方法包括在半导体衬底的器件区域上形成界面氧化物，氧氮化物和/或氮化物层，所述界面层的厚度小于10埃; 和（b）在所述界面氧化物，氧氮化物和/或氮化物层上形成高k电介质材料，所述高k电介质的介电常数k大于8。

公开(公告)号：US08716096B2

公开(公告)日：2014-05-06

申请号：US13323977

申请日：2011-12-13

申请人： Kevin K. Chan ,  David L. Harame ,  Russell T. Herrin ,  Qizhi Liu

发明人： Kevin K. Chan ,  David L. Harame ,  Russell T. Herrin ,  Qizhi Liu

IPC分类号： H01L21/331 ,  H01L21/8222

CPC分类号： H01L29/737 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7371

摘要： A self-aligned bipolar transistor and method of fabricating the same are disclosed. In an embodiment, a substrate and an intrinsic base are provided, followed by a first oxide layer, and an extrinsic base over the first oxide layer. A first opening is formed, exposing a portion of a surface of the extrinsic base. Sidewall spacers are formed in the first opening, and a self-aligned oxide mask is selectively formed on the exposed surface of the extrinsic base. The spacers are removed, and using the self-aligned oxide mask, the exposed extrinsic base and the first oxide layer are etched to expose the intrinsic base layer, forming a first and a second slot. A silicon layer stripe is selectively grown on the exposed intrinsic and/or extrinsic base layers in each of the first and second slots, substantially filling the respective slot.

摘要翻译： 公开了一种自对准双极晶体管及其制造方法。 在一个实施例中，提供衬底和本征基极，随后是第一氧化物层，以及在第一氧化物层上的外部基极。 形成第一开口，暴露外部基底的表面的一部分。 在第一开口中形成侧壁间隔物，并且在外基的暴露表面上选择性地形成自对准氧化物掩模。 去除间隔物，并且使用自对准氧化物掩模，暴露的非本征基底和第一氧化物层被蚀刻以暴露本征基底层，形成第一和第二狭槽。 在第一和第二槽中的每一个中的暴露的本征和/或非本征基极层上选择性地生长硅层条纹，基本上填充相应的槽。

公开(公告)号：US08603883B2

公开(公告)日：2013-12-10

申请号：US13297464

申请日：2011-11-16

申请人： Kevin K. Chan ,  Peng Cheng ,  Qizhi Liu ,  Ljubo Radic

发明人： Kevin K. Chan ,  Peng Cheng ,  Qizhi Liu ,  Ljubo Radic

IPC分类号： H01L21/331

CPC分类号： H01L29/73 ,  G06F17/5045 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7371

摘要： Methods of fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. A first portion of the intrinsic base layer is masked while a second portion of an intrinsic base layer is etched. As a consequence of the masking, the second portion of the intrinsic base layer is thinner than the first portion of the intrinsic base layer. An emitter and an extrinsic base layer are formed in respective contacting relationships with the first and second portions of the intrinsic base layer.

摘要翻译： 制造双极结型晶体管，双极结型晶体管以及双极结型晶体管的设计结构的方法。 本征基底层的第一部分被掩蔽，同时蚀刻本征基底层的第二部分。 作为掩蔽的结果，本征基底层的第二部分比本征基底层的第一部分薄。 在与本征基层的第一和第二部分分别的接触关系中形成发射极和非本征基层。

公开(公告)号：US20130119442A1

公开(公告)日：2013-05-16

申请号：US13294731

申请日：2011-11-11

申请人： Kevin K. Chan ,  John J. Ellis-Monaghan ,  David L. Harame ,  Qizhi Liu ,  John J. Pekarik

发明人： Kevin K. Chan ,  John J. Ellis-Monaghan ,  David L. Harame ,  Qizhi Liu ,  John J. Pekarik

IPC分类号： H01L21/337 ,  G06F17/50 ,  H01L29/808

CPC分类号： H01L29/8086 ,  G06F17/5045 ,  H01L27/0623 ,  H01L29/0817 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/1058 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/808

摘要： Junction field-effect transistors, methods for fabricating junction field-effect transistors, and design structures for a junction field-effect transistor. A source and a drain of the junction field-effect transistor are comprised of a semiconductor material grown by selective epitaxy and in direct contact with a top surface of a semiconductor layer. A gate is formed that is aligned with a channel laterally disposed in the semiconductor layer between the source and the drain. The source, the drain, and the semiconductor layer are each comprised of a second semiconductor material having an opposite conductivity type from a first semiconductor material comprising the gate.

摘要翻译： 结型场效应晶体管，用于制造结型场效应晶体管的方法，以及结型场效应晶体管的设计结构。 结场效应晶体管的源极和漏极由通过选择性外延生长并与半导体层的顶表面直接接触的半导体材料组成。 形成与在源极和漏极之间横向设置在半导体层中的沟道对准的栅极。 源极，漏极和半导体层各自包括与包括栅极的第一半导体材料具有相反导电类型的第二半导体材料。

公开(公告)号：US20120289018A1

公开(公告)日：2012-11-15

申请号：US13556372

申请日：2012-07-24

申请人： Tak H. Ning ,  Kevin K. Chan ,  Marwan H. Khater

发明人： Tak H. Ning ,  Kevin K. Chan ,  Marwan H. Khater

IPC分类号： H01L21/331

CPC分类号： H01L29/7317 ,  H01L27/0821 ,  H01L27/1203 ,  H01L29/0808 ,  H01L29/165 ,  H01L29/66265

摘要： A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area.

摘要翻译： 在绝缘体上半导体衬底上形成横向异质结双极晶体管（HBT）。 HBT包括基底，其包括掺杂的硅 - 锗合金基底区域，包括掺杂硅并且横向接触基底的发射体，以及包括掺杂硅并且横向接触基底的收集器。 因为集电极电流被引导通过掺杂的硅 - 锗基区，所以与使用硅沟道的可比较的双极晶体管相比，HBT可以容纳更大的电流密度。 基底还可以包括上硅基区和/或下硅基区。 在这种情况下，集电极电流集中在掺杂的硅 - 锗基区域中，从而最小化引入到基极周边的载流子散射的噪声。 此外，寄生电容被最小化，因为发射极 - 基极结面积与集电极 - 基极结面积相同。

公开(公告)号：US08198673B2

公开(公告)日：2012-06-12

申请号：US13080702

申请日：2011-04-06

申请人： Haizhou Yin ,  Xinhui Wang ,  Kevin K. Chan ,  Zhibin Ren

发明人： Haizhou Yin ,  Xinhui Wang ,  Kevin K. Chan ,  Zhibin Ren

IPC分类号： H01L21/00

CPC分类号： H01L21/26586 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7835

摘要： The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming a gate structure on top of a semiconductor substrate, the gate structure including a gate stack and spacers adjacent to sidewalls of the gate stack, and having a first side and a second side opposite to the first side; performing angled ion-implantation from the first side of the gate structure in the substrate, thereby forming an ion-implanted region adjacent to the first side, wherein the gate structure prevents the angled ion-implantation from reaching the substrate adjacent to the second side of the gate structure; and performing epitaxial growth on the substrate at the first and second sides of the gate structure. As a result, epitaxial growth on the ion-implanted region is much slower than a region experiencing no ion-implantation. A source region formed to the second side of the gate structure by the epitaxial growth has a height higher than a drain region formed to the first side of the gate structure by the epitaxial growth. A semiconductor structure formed thereby is also provided.

摘要翻译： 本发明提供了形成非对称场效应晶体管的方法。 该方法包括在半导体衬底的顶部上形成栅极结构，该栅极结构包括一个栅极叠层和邻近该栅极叠层的侧壁的间隔物，并具有与第一侧相对的第一侧和第二侧; 从衬底中的栅极结构的第一侧进行成角度的离子注入，从而形成与第一侧相邻的离子注入区域，其中栅极结构防止成角度的离子注入到达邻近第二侧的衬底 门结构; 以及在栅极结构的第一和第二侧在衬底上进行外延生长。 结果，在离子注入区域上的外延生长比经历无离子注入的区域慢得多。 通过外延生长形成到栅极结构的第二侧的源极区域的高度高于通过外延生长形成于栅极结构的第一侧的漏极区域的高度。 还提供了由此形成的半导体结构。