发明授权
US06908837B2 Method of manufacturing a semiconductor integrated circuit device including a gate electrode having a salicide layer thereon
有权
一种半导体集成电路器件的制造方法，其包括在其上具有自对准硅层的栅电极
- 专利标题： Method of manufacturing a semiconductor integrated circuit device including a gate electrode having a salicide layer thereon
- 专利标题（中）： 一种半导体集成电路器件的制造方法，其包括在其上具有自对准硅层的栅电极
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申请号： US10251849申请日： 2002-09-23
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公开(公告)号： US06908837B2公开(公告)日： 2005-06-21
- 发明人: Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
- 申请人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
- 申请人地址： JP Tokyo
- 专利权人： Renesas Technology Corp.
- 当前专利权人： Renesas Technology Corp.
- 当前专利权人地址： JP Tokyo
- 代理机构： Antonelli, Terry, Stout & Kraus, LLP
- 优先权： JP10-369017 19981225
- 主分类号： H01L27/04
- IPC分类号： H01L27/04 ; H01L21/336 ; H01L21/822 ; H01L21/8234 ; H01L21/8238 ; H01L21/8242 ; H01L21/8247 ; H01L27/092 ; H01L27/10 ; H01L27/105 ; H01L27/108 ; H01L29/78 ; H01L21/44
摘要：
A method of manufacturing a semiconductor integrated circuit device includes the steps of depositing a first insulating film over a first conductive layer, patterning the first insulating film by using a resist film as a mask to form a cap film, and removing the resist film. After which, a gate electrode of a MISFET is formed by etching the first conductive layer using the cap film as a mask. A second insulating film is deposited over the gate electrode and the cap film and a side wall spacer formed on side surfaces of the gate electrode by etching the second insulating film. After which, a salicide layer is selectively formed on the gate electrode. The cap film is removed by over-etching the first insulating film to etch the cap film.