Invention Grant
US06927123B2 Method for forming a self-aligned buried strap in a vertical memory cell
有权
在垂直存储单元中形成自对准掩埋带的方法
- Patent Title: Method for forming a self-aligned buried strap in a vertical memory cell
- Patent Title (中): 在垂直存储单元中形成自对准掩埋带的方法
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Application No.: US10846272Application Date: 2004-05-14
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Publication No.: US06927123B2Publication Date: 2005-08-09
- Inventor: Cheng-Chih Huang , Sheng-Wei Yang , Neng-Tai Shih , Chen-Chou Huang
- Applicant: Cheng-Chih Huang , Sheng-Wei Yang , Neng-Tai Shih , Chen-Chou Huang
- Applicant Address: TW Taoyuan
- Assignee: Nanya Technology Corporation
- Current Assignee: Nanya Technology Corporation
- Current Assignee Address: TW Taoyuan
- Agency: Quintero Law Office
- Priority: TW92134313A 20031205
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L21/8242 ; H01L29/94 ; H01L21/20

Abstract:
A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided, a capacitor wire is formed on the bottom portion of the trench, and a collar dielectric layer is formed between the capacitor wire and the semiconductor substrate to act as an isolation. The capacitor wire and the collar dielectric layer are etched to a predetermined depth, such that a gap is formed between the spacer and the capacitor wire and the collar dielectric layer. Ions are doped into the exposed semiconductor substrate to form an ion doped area acting as a buried strap. The spacer is removed, and an exposed collar dielectric layer is etched below the level of the surface of the capacitor wire, and a groove is formed between the capacitor wire and the trench sidewall to fill with a conducting layer.
Public/Granted literature
- US20050124110A1 METHOD FOR FORMING A SELF-ALIGNED BURIED STRAP IN A VERTICAL MEMORY CELL Public/Granted day:2005-06-09
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