Invention Grant
- Patent Title: Arrangement of integrated circuits in a memory module
- Patent Title (中): 集成电路在存储器模块中的布置
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Application No.: US10765488Application Date: 2004-01-27
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Publication No.: US06930903B2Publication Date: 2005-08-16
- Inventor: Jayesh R. Bhakta , Robert S. Pauley, Jr.
- Applicant: Jayesh R. Bhakta , Robert S. Pauley, Jr.
- Applicant Address: US CA Irvine
- Assignee: Netlist, Inc.
- Current Assignee: Netlist, Inc.
- Current Assignee Address: US CA Irvine
- Agency: Knobbe, Martens, Olson & Bear, LLP
- Main IPC: G11C5/00
- IPC: G11C5/00 ; H05K1/02 ; H05K1/18 ; G11C5/06 ; G06F12/00 ; G06F13/00 ; G11C5/02 ; G11C19/00

Abstract:
Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.
Public/Granted literature
- US20040184300A1 Arrangement of integrated circuits in a memory module Public/Granted day:2004-09-23
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