公开(公告)号：US07965579B1

公开(公告)日：2011-06-21

申请号：US12981380

申请日：2010-12-29

Applicant: Jeffrey C. Solomon ,  Jayesh R. Bhakta

Inventor： Jeffrey C. Solomon ,  Jayesh R. Bhakta

IPC: G11C8/00

Abstract: A circuit is configured to be mounted on a memory module configured to be operationally coupled to a computer system. The memory module has a first number of ranks of double-data-rate (DDR) memory devices configured to be activated concurrently with one another in response to a first number of chip-select signals. The circuit is configurable to receive a set of signals comprising address signals and a second number of chip-select signals, the address signals comprising bank address signals. The circuit is further configurable to monitor command signals received by the memory module, to selectively isolate a load of at least one rank of the first number of ranks from the computer system in response to the command signals, and to provide the first number of chip-select signals to the first number of ranks in response at least in part to the received bank address signals and the received second number of chip-select signals.

公开(公告)号：US20110090749A1

公开(公告)日：2011-04-21

申请号：US12954492

申请日：2010-11-24

Applicant: Jayesh R. Bhakta ,  Jeffrey C. Solomon

Inventor： Jayesh R. Bhakta ,  Jeffrey C. Solomon

IPC: G11C8/18 ,  G11C7/00

CPC classification number: G11C8/12 ,  G06F12/0207 ,  G06F12/0215 ,  G11C5/04 ,  G11C5/066 ,  G11C7/1048 ,  G11C2207/105 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2203/1572 ,  Y02P70/611

Abstract: A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated by a first number of chip-select signals. The circuit is configurable to receive bank address signals, a second number of chip-select signals, and row/column address signals from the computer system. The circuit is further configurable to generate phase-locked clock signals in response to clock signals received from the computer system and to provide the first number of chip-select signals to the first number of ranks in response to the phase-locked clock signals, the received bank address signals, the received second number of chip-select signals, and at least one of the received row/column address signals.

Abstract translation: 电路被配置为安装在可连接到计算机系统的存储器模块上，以便电耦合到存储器模块上的多个存储器件。 存储器模块具有由第一数量的芯片选择信号激活的第二数量的双数据速率（DDR）存储器件。 电路可配置为接收来自计算机系统的存储体地址信号，第二数量的芯片选择信号和行/列地址信号。 该电路还可配置为响应于从计算机系统接收的时钟信号而产生锁相时钟信号，并响应于锁相时钟信号将第一数量的芯片选择信号提供给第一数量的等级， 接收的存储体地址信号，所接收的第二数量的芯片选择信号，以及所接收的行/列地址信号中的至少一个。

公开(公告)号：US07630202B2

公开(公告)日：2009-12-08

申请号：US12052678

申请日：2008-03-20

Applicant: Robert S. Pauley ,  Jayesh R. Bhakta ,  William M. Gervasi ,  Chi She Chen ,  Jose Delvalle

Inventor： Robert S. Pauley ,  Jayesh R. Bhakta ,  William M. Gervasi ,  Chi She Chen ,  Jose Delvalle

IPC: H05K7/20

CPC classification number: H05K1/0203 ,  H05K1/144 ,  H05K2201/10189 ,  H05K2201/1056 ,  H05K2201/2018 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/4913

Abstract: A module is electrically connectable to a computer system. The module includes a plurality of electrical contacts which are electrically connectable to the computer system. The module further includes a first substrate which has a first surface and a first plurality of components mounted on the first surface. The first plurality of components is in electrical communication with the electrical contacts. The module further includes a second substrate which has a second surface and a second plurality of components mounted on the second surface. The second plurality of components is in electrical communication with the electrical contacts. The second surface of the second substrate faces the first surface of the first substrate. The module further includes at least one thermally conductive layer positioned between the first plurality of components and the second plurality of components. The at least one thermally conductive layer is in thermal communication with the first plurality of components, the second plurality of components, and a first set of the plurality of electrical contacts.

Abstract translation: 模块可电连接到计算机系统。 模块包括可电连接到计算机系统的多个电触点。 该模块还包括具有安装在第一表面上的第一表面和第一多个部件的第一基板。 第一组多个组件与电触点电连通。 该模块还包括具有安装在第二表面上的第二表面和第二多个部件的第二基板。 第二组件与电触点电连通。 第二基板的第二表面面向第一基板的第一表面。 模块还包括位于第一多个部件和第二多个部件之间的至少一个导热层。 所述至少一个导热层与所述第一多个部件，所述第二多个部件和所述多个电触点的第一组热连通。

公开(公告)号：US07532537B2

公开(公告)日：2009-05-12

申请号：US11335875

申请日：2006-01-19

Applicant: Jeffrey C. Solomon ,  Jayesh R. Bhakta

Inventor： Jeffrey C. Solomon ,  Jayesh R. Bhakta

IPC: G11C8/00

CPC classification number: G11C5/04 ,  G06F12/0207 ,  G06F12/0215 ,  G11C5/066 ,  G11C7/1048 ,  G11C8/12 ,  G11C2207/105 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2203/1572 ,  Y02D10/13 ,  Y02P70/611

Abstract: A memory module includes a plurality of memory devices and a circuit. Each memory device has a corresponding load. The circuit is electrically coupled to the plurality of memory devices and is configured to be electrically coupled to a memory controller of a computer system. The circuit selectively isolates one or more of the loads of the memory devices from the computer system. The circuit comprises logic which translates between a system memory domain of the computer system and a physical memory domain of the memory module.

公开(公告)号：US20080316712A1

公开(公告)日：2008-12-25

申请号：US12052678

申请日：2008-03-20

Applicant: Robert S. Pauley ,  Jayesh R. Bhakta ,  William M. Gervasi ,  Chi She Chen ,  Jose Delvalle

Inventor： Robert S. Pauley ,  Jayesh R. Bhakta ,  William M. Gervasi ,  Chi She Chen ,  Jose Delvalle

IPC: H05K7/20

CPC classification number: H05K1/0203 ,  H05K1/144 ,  H05K2201/10189 ,  H05K2201/1056 ,  H05K2201/2018 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/4913

Abstract: A module is electrically connectable to a computer system. The module includes a plurality of electrical contacts which are electrically connectable to the computer system. The module further includes a first substrate which has a first surface and a first plurality of components mounted on the first surface. The first plurality of components is in electrical communication with the electrical contacts. The module further includes a second substrate which has a second surface and a second plurality of components mounted on the second surface. The second plurality of components is in electrical communication with the electrical contacts. The second surface of the second substrate faces the first surface of the first substrate. The module further includes at least one thermally conductive layer positioned between the first plurality of components and the second plurality of components. The at least one thermally conductive layer is in thermal communication with the first plurality of components, the second plurality of components, and a first set of the plurality of electrical contacts.

Abstract translation: 模块可电连接到计算机系统。 模块包括可电连接到计算机系统的多个电触点。 该模块还包括具有安装在第一表面上的第一表面和第一多个部件的第一基板。 第一组多个组件与电触点电连通。 该模块还包括具有安装在第二表面上的第二表面和第二多个部件的第二基板。 第二组件与电触点电连通。 第二基板的第二表面面向第一基板的第一表面。 模块还包括位于第一多个部件和第二多个部件之间的至少一个导热层。 所述至少一个导热层与所述第一多个部件，所述第二多个部件和所述多个电触点的第一组热连通。

公开(公告)号：US06873534B2

公开(公告)日：2005-03-29

申请号：US10768534

申请日：2004-01-30

Applicant: Jayesh R. Bhakta ,  Robert S. Pauley, Jr.

Inventor： Jayesh R. Bhakta ,  Robert S. Pauley, Jr.

IPC: G11C5/00 ,  H05K1/02 ,  H05K1/18 ,  G11C5/06 ,  G06F12/00 ,  G06F13/00 ,  G11C5/02 ,  G11C19/00

CPC classification number: H05K1/181 ,  H05K1/0266 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2201/10689 ,  Y02P70/611

Abstract: Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.

公开(公告)号：US08345427B2

公开(公告)日：2013-01-01

申请号：US12939915

申请日：2010-11-04

Applicant: Robert S. Pauley ,  Jayesh R. Bhakta ,  William M. Gervasi ,  Chi She Chen ,  Jose Delvalle

Inventor： Robert S. Pauley ,  Jayesh R. Bhakta ,  William M. Gervasi ,  Chi She Chen ,  Jose Delvalle

IPC: H05K7/20

CPC classification number: H05K1/0203 ,  H05K1/144 ,  H05K2201/10189 ,  H05K2201/1056 ,  H05K2201/2018 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/4913

Abstract: A module is electrically connectable to a computer system. The module includes a first surface and a first plurality of circuit packages coupled to the first surface. The module further includes a second surface and a second plurality of circuit packages coupled to the second surface. The second surface faces the first surface. The module further includes at least one thermal conduit positioned between the first surface and the second surface. The at least one thermal conduit is in thermal communication with the first plurality of circuit packages and the second plurality of circuit packages.

Abstract translation: 模块可电连接到计算机系统。 模块包括耦合到第一表面的第一表面和第一多个电路封装。 该模块还包括耦合到第二表面的第二表面和第二多个电路封装。 第二表面面向第一表面。 模块还包括位于第一表面和第二表面之间的至少一个热导管。 所述至少一个热导管与所述第一多个电路封装件和所述第二多个电路封装体热连通。

公开(公告)号：US08264903B1

公开(公告)日：2012-09-11

申请号：US12774632

申请日：2010-05-05

Applicant: Hyun Lee ,  Jayesh R. Bhakta

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G11C7/00

CPC classification number: G11C11/40618 ,  G11C5/04 ,  G11C11/40611

Abstract: A memory module according to certain aspects has a plurality of memory devices arranged into one or more logical ranks. Each logical rank may correspond to a set of at least two physical ranks. The memory module can include a circuit operatively coupled to the plurality of memory devices and configured to be operatively coupled to a memory controller of a computer system to receive a logical rank refresh command. In response, the circuit can initiate a first refresh operation for one or more first physical ranks and then initiate a second refresh operation for one or more second physical ranks. The memory module can further include a memory location storing a refresh time (tRFC) value accessible by the memory controller and based at least in part on a calculated maximum amount of time for refreshing the logical rank.

Abstract translation: 根据某些方面的存储器模块具有布置成一个或多个逻辑等级的多个存储器件。 每个逻辑等级可以对应于一组至少两个物理等级。 存储器模块可以包括可操作地耦合到多个存储器件并且被配置为可操作地耦合到计算机系统的存储器控​​制器以接收逻辑秩刷新命令的电路。 作为响应，电路可以针对一个或多个第一物理等级启动第一刷新操作，然后针对一个或多个第二物理等级启动第二刷新操作。 存储器模块还可以包括存储位置，存储由存储器控制器可访问的刷新时间（tRFC）值，并至少部分地基于所计算的用于刷新逻辑等级的最大时间量。

公开(公告)号：US08081535B2

公开(公告)日：2011-12-20

申请号：US12954492

申请日：2010-11-24

Applicant: Jayesh R. Bhakta ,  Jeffrey C. Solomon

Inventor： Jayesh R. Bhakta ,  Jeffrey C. Solomon

IPC: G11C8/00

CPC classification number: G11C8/12 ,  G06F12/0207 ,  G06F12/0215 ,  G11C5/04 ,  G11C5/066 ,  G11C7/1048 ,  G11C2207/105 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2203/1572 ,  Y02P70/611

Abstract: A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated by a first number of chip-select signals. The circuit is configurable to receive bank address signals, a second number of chip-select signals, and row/column address signals from the computer system. The circuit is further configurable to generate phase-locked clock signals in response to clock signals received from the computer system and to provide the first number of chip-select signals to the first number of ranks in response to the phase-locked clock signals, the received bank address signals, the received second number of chip-select signals, and at least one of the received row/column address signals.

Abstract translation: 电路被配置为安装在可连接到计算机系统的存储器模块上，以便电耦合到存储器模块上的多个存储器件。 存储器模块具有由第一数量的芯片选择信号激活的第二数量的双数据速率（DDR）存储器件。 电路可配置为接收来自计算机系统的存储体地址信号，第二数量的芯片选择信号和行/列地址信号。 该电路还可配置为响应于从计算机系统接收的时钟信号而产生锁相时钟信号，并响应于锁相时钟信号将第一数量的芯片选择信号提供给第一数量的等级， 接收的存储体地址信号，所接收的第二数量的芯片选择信号，以及所接收的行/列地址信号中的至少一个。

公开(公告)号：US08033836B1

公开(公告)日：2011-10-11

申请号：US12874900

申请日：2010-09-02

Applicant: Jayesh R. Bhakta ,  Enchao Yu ,  Chi She Chen ,  Richard E. Flaig

Inventor： Jayesh R. Bhakta ,  Enchao Yu ,  Chi She Chen ,  Richard E. Flaig

IPC: H01R12/00

CPC classification number: H05K1/147 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/0203 ,  H05K1/141 ,  H05K3/4691 ,  H05K2201/10159 ,  H05K2201/1056 ,  H05K2203/1572 ,  H01L2224/0401

Abstract: A circuit includes a first plurality of contacts configured to be in electrical communication with a plurality of electronic devices. The circuit card further includes a flexible portion including a dielectric layer, a second plurality of contacts, and a plurality of electrical conduits extending across a region of the flexible portion and in electrical communication with one or more contacts of the first plurality of contacts and with the second plurality of contacts. The flexible portion further includes an electrically conductive layer extending across the region of the flexible portion. The electrically conductive layer is superposed with the plurality of electrical conduits with the dielectric layer therebetween. The electrically conductive layer does not overlay one or more portions of the dielectric layer in the region of the flexible portion.

Abstract translation: 电路包括构造成与多个电子设备电连通的第一多个触点。 电路卡还包括柔性部分，该柔性部分包括电介质层，第二多个触点以及跨越柔性部分的区域延伸并且与第一多个触点的一个或多个触点电连通并且与 第二个多个联系人。 柔性部分还包括延伸穿过柔性部分的区域的导电层。 导电层与多个电导管重叠，其间具有介电层。 在柔性部分的区域中，导电层不覆盖电介质层的一个或多个部分。