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US06960808B2 Semiconductor device having a lower parasitic capacitance 失效
具有较低寄生电容的半导体器件

Semiconductor device having a lower parasitic capacitance
Abstract:
A method for fabricating a semiconductor device is described. A gate dielectric layer is formed on a substrate, and several gate structures having a gate conductor, a cap layer and spacers are formed on the gate dielectric layer. A mask layer is formed over the substrate covering a portion of the gate structures. Removing the cap layer and spacers that are not covered by the mask layer. After the mask layer is removed, a dielectric layer is formed over the substrate covering the gate structures. A self-aligned contact-hole is formed in the dielectric layer. A conductive layer is formed in the self-aligned contact hole and on the dielectric layer. Since the cap layer and spacers that are not covered by the mask layer are removed and substituted by the dielectric layer having lowerdielectric constant property, the parasitic capacitance can be reduced.
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