Invention Grant
- Patent Title: Semiconductor device having a lower parasitic capacitance
- Patent Title (中): 具有较低寄生电容的半导体器件
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Application No.: US10707358Application Date: 2003-12-08
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Publication No.: US06960808B2Publication Date: 2005-11-01
- Inventor: Yu-Piao Wang
- Applicant: Yu-Piao Wang
- Applicant Address: TW Hsinchu
- Assignee: ProMOS Technologies Inc.
- Current Assignee: ProMOS Technologies Inc.
- Current Assignee Address: TW Hsinchu
- Agency: Jianq Chyun IP Office
- Priority: TW92123253A 20030825
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L21/336 ; H01L21/60 ; H01L21/768 ; H01L21/8234 ; H01L23/522 ; H01L29/76 ; H01L27/108 ; H01L29/94 ; H01L31/062 ; H01L31/113

Abstract:
A method for fabricating a semiconductor device is described. A gate dielectric layer is formed on a substrate, and several gate structures having a gate conductor, a cap layer and spacers are formed on the gate dielectric layer. A mask layer is formed over the substrate covering a portion of the gate structures. Removing the cap layer and spacers that are not covered by the mask layer. After the mask layer is removed, a dielectric layer is formed over the substrate covering the gate structures. A self-aligned contact-hole is formed in the dielectric layer. A conductive layer is formed in the self-aligned contact hole and on the dielectric layer. Since the cap layer and spacers that are not covered by the mask layer are removed and substituted by the dielectric layer having lowerdielectric constant property, the parasitic capacitance can be reduced.
Public/Granted literature
- US20050045865A1 [SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF] Public/Granted day:2005-03-03
Information query
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