Invention Grant
US07187000B2 High performance tunneling-biased MOSFET and a process for its manufacture 有权
高性能隧道偏置MOSFET及其制造工艺

High performance tunneling-biased MOSFET and a process for its manufacture
Abstract:
A semiconductor structure and a method for its manufacture are provided. In one example, the structure includes a well region doped with a first type dopant (e.g., a P-type or N-type dopant). A gate pedestal formed over the well region has two ends, one of which at least partially overlies the well region and is doped with the first type dopant. A dielectric layer is positioned between the gate pedestal and the well region. Source and drain regions formed on opposite sides of the gate pedestal within the well region are doped with a second type dopant opposite in type to the first type dopant.
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