公开(公告)号：US20060208316A1

公开(公告)日：2006-09-21

申请号：US11081993

申请日：2005-03-16

Applicant: Kuo-Nan Yang ,  Yi-Ling Chang ,  You-Lin Chu ,  Hou-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

Inventor： Kuo-Nan Yang ,  Yi-Ling Chang ,  You-Lin Chu ,  Hou-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

IPC: H01L29/94

CPC classification number: H01L29/88 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a method for its manufacture are provided. In one example, the structure includes a well region doped with a first type dopant (e.g., a P-type or N-type dopant). A gate pedestal formed over the well region has two ends, one of which at least partially overlies the well region and is doped with the first type dopant. A dielectric layer is positioned between the gate pedestal and the well region. Source and drain regions formed on opposite sides of the gate pedestal within the well region are doped with a second type dopant opposite in type to the first type dopant.

Abstract translation: 提供半导体结构及其制造方法。 在一个示例中，该结构包括掺杂有第一类型掺杂剂的阱区（例如，P型或N型掺杂剂）。 形成在阱区上方的栅极基座具有两个端部，其中一个端部至少部分地覆盖阱区域并且掺杂有第一类型的掺杂剂。 电介质层位于门基座和阱区之间。 形成在阱区内的栅极基座的相对侧上的源极和漏极区域掺杂有与第一类型掺杂物类型相反的第二类型掺杂物。

公开(公告)号：US06674130B2

公开(公告)日：2004-01-06

申请号：US10316601

申请日：2002-12-11

Applicant: Kuo-Nan Yang ,  Yi-Ling Chan ,  You-Lin Chu ,  Hou-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

Inventor： Kuo-Nan Yang ,  Yi-Ling Chan ,  You-Lin Chu ,  Hou-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

IPC: H01L2362

CPC classification number: H01L29/4983 ,  H01L29/0895 ,  H01L29/1041 ,  H01L29/1083 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78612 ,  H01L2924/0002 ,  Y10S438/979 ,  H01L2924/00

Abstract: A new type of partially-depleted SOI MOSFET is described in which a tunneling connection between the gate and the base is introduced. This is achieved by using a gate dielectric whose thickness is below its tunneling threshold. The gate pedestal is made somewhat longer than normal and a region near one end is implanted to be P+ (or N+ in a PMOS device). This allows holes (electrons for PMOS) to tunnel from gate to base. Since the hole current is self limiting, applied voltages greater than 0.7 volts may be used without incurring excessive leakage (as is the case with prior art DTMOS devices). A process for manufacturing the device is also described.

Abstract translation: 描述了一种新型的部分耗尽的SOI MOSFET，其中引入了栅极和基极之间的隧道连接。 这通过使用其厚度低于其隧道阈值的栅极电介质实现。 栅极基座比正常长一些，一端附近的区域植入P +（或PMOS器件中的N +）。 这允许空穴（PMOS的电子）从栅极到基极隧道。 由于空穴电流是自限制的，所以可以使用大于0.7伏的施加电压，而不会引起过大的泄漏（如现有技术的DTMOS器件的情况）。 还描述了用于制造该装置的方法。

公开(公告)号：US07187000B2

公开(公告)日：2007-03-06

申请号：US11081993

申请日：2005-03-16

Applicant: Kuo-Nan Yang ,  Yi-Ling Chang ,  You-Lin Chu ,  Hou-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

Inventor： Kuo-Nan Yang ,  Yi-Ling Chang ,  You-Lin Chu ,  Hou-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

IPC: H01L23/62 ,  H01L29/10

CPC classification number: H01L29/88 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a method for its manufacture are provided. In one example, the structure includes a well region doped with a first type dopant (e.g., a P-type or N-type dopant). A gate pedestal formed over the well region has two ends, one of which at least partially overlies the well region and is doped with the first type dopant. A dielectric layer is positioned between the gate pedestal and the well region. Source and drain regions formed on opposite sides of the gate pedestal within the well region are doped with a second type dopant opposite in type to the first type dopant.

Abstract translation: 提供半导体结构及其制造方法。 在一个示例中，该结构包括掺杂有第一类型掺杂剂的阱区（例如，P型或N型掺杂剂）。 形成在阱区上方的栅极基座具有两个端部，其中一个端部至少部分地覆盖阱区域并且掺杂有第一类型的掺杂剂。 电介质层位于门基座和阱区之间。 形成在阱区内的栅极基座的相对侧上的源极和漏极区域掺杂有与第一类型掺杂物类型相反的第二类型掺杂物。

公开(公告)号：US06518105B1

公开(公告)日：2003-02-11

申请号：US10021702

申请日：2001-12-10

Applicant: Kuo-Nan Yang ,  Yi-Ling Chan ,  You-Lin Chu ,  Hou-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

Inventor： Kuo-Nan Yang ,  Yi-Ling Chan ,  You-Lin Chu ,  Hou-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

IPC: H01L2100

CPC classification number: H01L29/4983 ,  H01L29/0895 ,  H01L29/1041 ,  H01L29/1083 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78612 ,  H01L2924/0002 ,  Y10S438/979 ,  H01L2924/00

Abstract: A new type of partially-depleted SOI MOSFET is described in which a tunneling connection between the gate and the base is introduced. This is achieved by using a gate dielectric whose thickness is below its tunneling threshold. The gate pedestal is made somewhat longer than normal and a region near one end is implanted to be P+ (or N+ in a PMOS device). This allows holes (electrons for PMOS) to tunnel from gate to base. Since the hole current is self limiting, applied voltages greater than 0.7 volts may be used without incurring excessive leakage (as is the case with prior art DTMOS devices). A process for manufacturing the device is also described.

Abstract translation: 描述了一种新型的部分耗尽的SOI MOSFET，其中引入了栅极和基极之间的隧道连接。 这通过使用其厚度低于其隧道阈值的栅极电介质实现。 栅极基座比正常长一些，一端附近的区域植入P +（或PMOS器件中的N +）。 这允许空穴（PMOS的电子）从栅极到基极隧道。 由于空穴电流是自限制的，所以可以使用大于0.7伏的施加电压，而不会引起过大的泄漏（如现有技术的DTMOS器件的情况）。 还描述了用于制造该装置的方法。