公开(公告)号：US09350686B2

公开(公告)日：2016-05-24

申请号：US12466753

申请日：2009-05-15

Applicant: Kuo-Nan Yang ,  Chia-Hua Hsu ,  Fong-Ray Gu ,  Yen-Hsu Shih

Inventor： Kuo-Nan Yang ,  Chia-Hua Hsu ,  Fong-Ray Gu ,  Yen-Hsu Shih

IPC: G06F13/14 ,  H04L12/879 ,  H04L12/861

CPC classification number: H04L49/901 ,  H04L49/90 ,  H04L49/9073

Abstract: A data access device for a communication system includes: a write controller controlled by the host and outputting a write pointer; a read controller controlled by the write pointer and outputting a read pointer; a download timing controller comparing the write and read pointers to determine a timing of downloading data from the host, and including a pointer difference calculator and a comparator, the pointer difference calculator calculating a distance between the write and read pointers to obtain a pointer difference, the comparator outputting a download status indication according to the pointer difference and a first predetermined length to provide a basis for changing the write pointer; and a transmit buffer downloading data from the host according to the write pointer and transmitting data to the network interface according to the read pointer. A data access device for a network interface controller and a data access method are also disclosed.

Abstract translation: 一种用于通信系统的数据访问装置，包括：由主机控制并输出写指针的写控制器; 读写控制器，由写指针控制并输出读指针; 下载定时控制器，比较写入指针和读取指针，以确定从主机下载数据的定时，并且包括指针差分计算器和比较器，指针差分计算器计算写入和读取指针之间的距离以获得指针差异， 比较器根据指针差和第一预定长度输出下载状态指示，以提供改变写指针的基础; 以及发送缓冲器，根据写指针从主机下载数据，并根据读指针将数据发送到网络接口。 还公开了一种用于网络接口控制器和数据访问方法的数据访问装置。

公开(公告)号：US09319353B2

公开(公告)日：2016-04-19

申请号：US12491219

申请日：2009-06-24

Applicant: Li-Han Liang ,  Tao-Chun Wang ,  Kuo-Nan Yang ,  Shieh-Hsing Kuo

Inventor： Li-Han Liang ,  Tao-Chun Wang ,  Kuo-Nan Yang ,  Shieh-Hsing Kuo

IPC: H04L29/06 ,  H04K1/00 ,  H04L12/861 ,  G06F21/62

CPC classification number: H04L49/90 ,  G06F21/6218 ,  G06F2221/2107 ,  H04L49/9057 ,  H04L63/0428 ,  H04L63/0442 ,  H04L63/0485

Abstract: A network task offload apparatus includes an offload circuit and a buffer scheduler. The offload circuit performs corresponding network task processing on a plurality of packets in parallel according to an offload command. The buffer scheduler includes a buffer control unit and a plurality of buffer units. The plurality of buffer units are controlled by the buffer control unit and are scheduled to store the processed packets.

Abstract translation: 网络任务卸载装置包括卸载电路和缓冲器调度器。 卸载电路根据卸载命令并行地对多个分组进行相应的网络任务处理。 缓冲器调度器包括缓冲器控制单元和多个缓冲单元。 多个缓冲单元由缓冲器控制单元控制，并被调度以存储经处理的分组。

公开(公告)号：US08547985B2

公开(公告)日：2013-10-01

申请号：US12942677

申请日：2010-11-09

Applicant: Kuo-Nan Yang ,  Yen-Hsu Shih ,  Chia-Ying Chiu ,  Kai-Wen Cheng

Inventor： Kuo-Nan Yang ,  Yen-Hsu Shih ,  Chia-Ying Chiu ,  Kai-Wen Cheng

IPC: H04L12/28

CPC classification number: H04L49/9078 ,  H04L49/901 ,  H04L49/9047 ,  H04L49/9057

Abstract: The disclosure is a network interface controller (NIC) capable of sharing buffers, which is coupled to a host and a network to make the network connection. The NIC includes a transmitting buffer, a transmitting controller, a receiving buffer, and a receiving controller. The transmitting controller controls the transmitting buffer to transmit the transmission data provided by the host to the network. The receiving controller controls the receiving buffer to transmit the reception data received from the network to the host, and determines a storage capacity of the receiving buffer. When the storage capacity is smaller than a set value, the receiving controller transmits a request signal to the transmitting controller, the transmitting controller generates a response signal according to the request signal and a status signal corresponding to the transmitting buffer, and the receiving controller controls whether reception data is stored in the transmitting buffer according to the response signal.

Abstract translation: 本公开是能够共享缓冲器的网络接口控制器（NIC），其耦合到主机和网络以进行网络连接。 NIC包括发送缓冲器，发送控制器，接收缓冲器和接收控制器。 发送控制器控制发送缓冲器将由主机提供的发送数据发送到网络。 接收控制器控制接收缓冲器将从网络接收的接收数据发送到主机，并确定接收缓冲器的存储容量。 当存储容量小于设定值时，接收控制器向发送控制器发送请求信号，发送控制器根据请求信号和对应于发送缓冲器的状态信号生成响应信号，接收控制器控制 接收数据是否根据响应信号存储在发送缓冲器中。

公开(公告)号：US20110283068A1

公开(公告)日：2011-11-17

申请号：US13107279

申请日：2011-05-13

Applicant: Chien-Ping HUNG ,  Fong-Ray GU ,  Chia-Hung LIN ,  Kuo-Nan YANG

Inventor： Chien-Ping HUNG ,  Fong-Ray GU ,  Chia-Hung LIN ,  Kuo-Nan YANG

IPC: G06F12/00

CPC classification number: G06F13/28

Abstract: A memory access apparatus is coupled to a memory unit and includes a header access circuit and a payload access circuit. The header access circuit includes a header fetching unit used to fetch a header descriptor in the memory unit, and the payload access circuit includes a payload fetching unit used to fetch a payload descriptor in the memory unit. The header access circuit and the payload access circuit perform fetching with respect to the memory unit in a non-sequenced manner.

Abstract translation: 存储器访问装置耦合到存储器单元，并且包括标题存取电路和有效载荷存取电路。 标题访问电路包括用于获取存储器单元中的报头描述符的报头获取单元，并且有效载荷访问电路包括用于在存储器单元中获取有效载荷描述符的有效载荷提取单元。 标题访问电路和有效载荷访问电路以非顺序的方式执行相对于存储器单元的提取。

公开(公告)号：US07943986B2

公开(公告)日：2011-05-17

申请号：US11761547

申请日：2007-06-12

Applicant: Kuo-Nan Yang ,  Yi-Lang Chen ,  Hou-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

Inventor： Kuo-Nan Yang ,  Yi-Lang Chen ,  Hou-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

IPC: H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/78615

Abstract: A method for fabricating a Finfet device with body contacts and a device fabricated using the method are provided. In one example, a silicon-on-insulator substrate is provided. A T-shaped active region is defined in the silicon layer of the silicon-on-insulator substrate. A source region and a drain region form two ends of a cross bar of the T-shaped active region and a body contact region forms a leg of the T-shaped active region. A gate oxide layer is grown on the active region. A polysilicon layer is deposited overlying the gate oxide layer and patterned to form a gate, where an end of the gate partially overlies the body contact region to complete formation of a Finfet device with body contact.

Abstract translation: 提供了一种用于制造具有主体触点的Finfet器件的方法和使用该方法制造的器件。 在一个示例中，提供绝缘体上硅衬底。 在绝缘体上硅衬底的硅层中限定T形有源区。 源极区域和漏极区域形成T形有源区域的横杆的两个端部，并且主体接触区域形成T形有源区域的腿部。 在有源区上生长栅氧化层。 沉积覆盖栅极氧化物层的多晶硅层并图案化以形成栅极，其中栅极的一端部分覆盖在主体接触区域上，以完成具有身体接触的Finfet器件的形成。

公开(公告)号：US20090292836A1

公开(公告)日：2009-11-26

申请号：US12466753

申请日：2009-05-15

Applicant: Kuo-Nan Yang ,  Chia-Hua Hsu ,  Fong-Ray Gu ,  Yen-Hsu Shih

Inventor： Kuo-Nan Yang ,  Chia-Hua Hsu ,  Fong-Ray Gu ,  Yen-Hsu Shih

IPC: G06F13/28 ,  G06F3/00

CPC classification number: H04L49/901 ,  H04L49/90 ,  H04L49/9073

Abstract: A data access device for a communication system includes: a write controller controlled by the host and outputting a write pointer; a read controller controlled by the write pointer and outputting a read pointer; a download timing controller comparing the write and read pointers to determine a timing of downloading data from the host, and including a pointer difference calculator and a comparator, the pointer difference calculator calculating a distance between the write and read pointers to obtain a pointer difference, the comparator outputting a download status indication according to the pointer difference and a first predetermined length to provide a basis for changing the write pointer; and a transmit buffer downloading data from the host according to the write pointer and transmitting data to the network interface according to the read pointer. A data access device for a network interface controller and a data access method are also disclosed.

Abstract translation: 一种用于通信系统的数据访问装置，包括：由主机控制并输出写指针的写控制器; 读写控制器，由写指针控制并输出读指针; 下载定时控制器，比较写入指针和读取指针，以确定从主机下载数据的定时，并且包括指针差分计算器和比较器，指针差分计算器计算写入和读取指针之间的距离以获得指针差异， 比较器根据指针差和第一预定长度输出下载状态指示，以提供改变写指针的基础; 以及发送缓冲器，根据写指针从主机下载数据，并根据读指针将数据发送到网络接口。 还公开了一种用于网络接口控制器和数据访问方法的数据访问装置。

公开(公告)号：US20070063261A1

公开(公告)日：2007-03-22

申请号：US11548772

申请日：2006-10-12

Applicant: Haur-Ywh CHEN ,  Fang-Cheng CHEN ,  Yi-Ling CHAN ,  Kuo-Nan YANG ,  Fu-Liang YANG ,  Chenming HU

Inventor： Haur-Ywh CHEN ,  Fang-Cheng CHEN ,  Yi-Ling CHAN ,  Kuo-Nan YANG ,  Fu-Liang YANG ,  Chenming HU

IPC: H01L29/788 ,  H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC classification number: H01L29/785 ,  H01L29/665 ,  H01L29/66795

Abstract: A method of fabricating a double gate, FINFET device structure in a silicon on insulator layer, in which the channel region formed in the SOI layer is defined with a narrowed, or necked shape, and wherein a composite insulator spacer is formed on the sides of the device structure, has been developed. A FINFET device structure shape is formed in an SOI layer via anisotropic RIE procedures, followed by a growth of a silicon dioxide gate insulator layer on the sides of the FINFET device structure shape. A gate structure is fabricated traversing the device structure and overlying the silicon dioxide gate insulator layer located on both sides of the narrowest portion of channel region. After formation of a source/drain region in wider, non-channel regions of the FINFET device structure shape, composite insulator spacers are formed on the sides of the FINFET shape and on the sides of the gate structure. Metal silicide is next formed on source/drain regions resulting in a FINFET device structure featuring a narrow channel region, and surrounded by composite insulator spacers located on the sides of the device structure.

Abstract translation: 一种在绝缘体上硅层制造双栅极FINFET器件结构的方法，其中形成在SOI层中的沟道区域被限定为窄的或颈部形状，并且其中复合绝缘体隔离物形成在 器件结构，已经开发。 通过各向异性RIE工艺在SOI层中形成FINFET器件结构形状，随后在FINFET器件结构形状的侧面上生长二氧化硅栅极绝缘体层。 制造横跨器件结构并覆盖位于沟道区域最窄部分两侧的二氧化硅栅极绝缘体层的栅极结构。 在FINFET器件结构形状的较宽的非沟道区域中形成源极/漏极区域之后，在FINFET形状的侧面和栅极结构的侧面上形成复合绝缘体间隔物。 金属硅化物接着形成在源极/漏极区域上，导致FINFET器件结构的特征是窄的沟道区域，并被位于器件结构侧面的复合绝缘体隔离物围绕。

公开(公告)号：US07122412B2

公开(公告)日：2006-10-17

申请号：US10835789

申请日：2004-04-30

Applicant: Haur-Ywh Chen ,  Fang-Cheng Chen ,  Yi-Ling Chan ,  Kuo-Nan Yang ,  Fu-Liang Yang ,  Chenming Hu

Inventor： Haur-Ywh Chen ,  Fang-Cheng Chen ,  Yi-Ling Chan ,  Kuo-Nan Yang ,  Fu-Liang Yang ,  Chenming Hu

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L29/785 ,  H01L29/665 ,  H01L29/66795

Abstract: A method of fabricating a double gate, FINFET device structure in a silicon on insulator layer, in which the channel region formed in the SOI layer is defined with a narrowed, or necked shape, and wherein a composite insulator spacer is formed on the sides of the device structure, has been developed. A FINFET device structure shape is formed in an SOI layer via anisotropic RIE procedures, followed by a growth of a silicon dioxide gate insulator layer on the sides of the FINFET device structure shape. A gate structure is fabricated traversing the device structure and overlying the silicon dioxide gate insulator layer located on both sides of the narrowest portion of channel region. After formation of a source/drain region in wider, non-channel regions of the FINFET device structure shape, composite insulator spacers are formed on the sides of the FINFET shape and on the sides of the gate structure. Metal silicide is next formed on source/drain regions resulting in a FINFET device structure featuring a narrow channel region, and surrounded by composite insulator spacers located on the sides of the device structure.

Abstract translation: 一种在绝缘体上硅层制造双栅极FINFET器件结构的方法，其中形成在SOI层中的沟道区域被限定为窄的或颈部形状，并且其中复合绝缘体隔离物形成在 器件结构，已经开发。 通过各向异性RIE工艺在SOI层中形成FINFET器件结构形状，随后在FINFET器件结构形状的侧面上生长二氧化硅栅极绝缘体层。 制造横跨器件结构并覆盖位于沟道区域最窄部分两侧的二氧化硅栅极绝缘体层的栅极结构。 在FINFET器件结构形状的较宽的非沟道区域中形成源极/漏极区域之后，在FINFET形状的侧面和栅极结构的侧面上形成复合绝缘体间隔物。 金属硅化物接着形成在源极/漏极区域上，导致FINFET器件结构的特征是窄的沟道区域，并被位于器件结构侧面的复合绝缘体隔离物围绕。

公开(公告)号：US06812116B2

公开(公告)日：2004-11-02

申请号：US10318454

申请日：2002-12-13

Applicant: Chien-Chao Huang ,  Yee-Chia Yeo ,  Kuo-Nan Yang ,  Chun-Chieh Lin ,  Chenming Hu

Inventor： Chien-Chao Huang ,  Yee-Chia Yeo ,  Kuo-Nan Yang ,  Chun-Chieh Lin ,  Chenming Hu

IPC: H01L21301

CPC classification number: H01L21/3247 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/02664 ,  H01L21/324 ,  H01L21/76259 ,  H01L29/1054

Abstract: A method for making a SOI wafer with a strained silicon layer for increased electron and hole mobility is achieved. The method forms a porous silicon layer on a seed wafer. A H2 anneal is used to form a smooth surface on the porous silicon. A strain free (relaxed) epitaxial SixGe1−x layer is deposited and a bonding layer is formed. The seed wafer is then bonded to a handle wafer having an insulator on the surface. A spray etch is used to etch the porous Si layer resulting in a SOI handle wafer having portions of the porous Si layer on the relaxed SixGe1−x. The handle wafer is then annealed in H2 to convert the porous Si to a smooth strained Si layer on the relaxed SiGe layer of the SOI wafer.

Abstract translation: 实现了制造具有用于增加电子和空穴迁移率的应变硅层的SOI晶片的方法。 该方法在种子晶片上形成多孔硅层。 使用H2退火在多孔硅上形成光滑表面。 沉积无应变的（松弛的）外延六面体Ge-x层并形成结合层。 然后将种子晶片结合到在表面上具有绝缘体的手柄晶片。 使用喷涂蚀刻来蚀刻多孔Si层，导致SOI处理晶片，其具有在松弛的SixGe1-x上的多孔Si层的部分。 然后将处理晶片在H 2中退火以将多孔Si转化为SOI晶片的松弛SiGe层上的平滑应变Si层。

公开(公告)号：US06784071B2

公开(公告)日：2004-08-31

申请号：US10355872

申请日：2003-01-31

Applicant: Haur-Ywh Chen ,  Yi-Ling Chan ,  Kuo-Nan Yang ,  Fu-Liang Yang ,  Chenming Hu

Inventor： Haur-Ywh Chen ,  Yi-Ling Chan ,  Kuo-Nan Yang ,  Fu-Liang Yang ,  Chenming Hu

IPC: H01L2130

CPC classification number: H01L21/76251 ,  Y10S438/977

Abstract: A new silicon structure is provided. Under a first embodiment of the invention, a first silicon substrate having a crystallographic orientation is bonded to the surface of a second silicon substrate having a crystallographic orientation, the wafer alignment notch of the first and the second silicon substrates are aligned with each other. Under a first embodiment of the invention, a first silicon substrate having a crystallographic orientation is bonded to the surface of a second silicon substrate having a crystallographic orientation, the wafer alignment notch of the first and the second silicon substrates are not aligned with each other.

Abstract translation: 提供了新的硅结构。 在本发明的第一实施例中，具有<100>晶体取向的第一硅衬底被结合到具有<110>晶体取向的第二硅衬底的表面上，第一和第二硅衬底的晶片对准凹槽是 彼此对齐。 在本发明的第一实施例中，具有<100>晶体取向的第一硅衬底被结合到具有<110>晶体取向的第二硅衬底的表面上，第一和第二硅衬底的晶片对准凹槽是 不对齐。