Invention Grant
- Patent Title: Semiconductor test device having clock recovery circuit
- Patent Title (中): 具有时钟恢复电路的半导体测试装置
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Application No.: US10512296Application Date: 2003-04-21
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Publication No.: US07187192B2Publication Date: 2007-03-06
- Inventor: Hideyuki Oshima , Yasutaka Tsuruki
- Applicant: Hideyuki Oshima , Yasutaka Tsuruki
- Applicant Address: JP Tokyo
- Assignee: Advantest Corp.
- Current Assignee: Advantest Corp.
- Current Assignee Address: JP Tokyo
- Agency: Muramatsu & Associates
- Priority: JP2002-126551 20020426
- International Application: PCT/JP03/05044 WO 20030421
- International Announcement: WO03/091742 WO 20031106
- Main IPC: G01R31/26
- IPC: G01R31/26 ; G01R31/28 ; G01R31/02

Abstract:
A semiconductor test device for acquiring a multiplexed clock signal from LSI output data and using the clock to test the LSI. The device includes a time interpolator and registers connected in series. The time interpolator has flip-flops connected in parallel for receiving output data from an LSI under test, a delay circuit for successively inputting strobes delayed at a constant timing interval to the flip-flops and outputting time-series level data, and an encoder for receiving the time-series level data from the flip-flops and encoding it into position data indicating an edge timing. The registers successively store position data from the encoder and output them at a predetermined timing. The device further includes a digital filter for outputting the position data from the registers as a recovery clock.
Public/Granted literature
- US20050156622A1 Semiconductor test device Public/Granted day:2005-07-21
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