发明授权
- 专利标题: Design method for semiconductor integrated circuit suppressing power supply noise
- 专利标题(中): 半导体集成电路抑制电源噪声的设计方法
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申请号: US11024470申请日: 2004-12-30
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公开(公告)号: US07278124B2公开(公告)日: 2007-10-02
- 发明人: Kenji Shimazaki , Kazuhiro Sato , Takahiro Ichinomiya , Shozo Hirano , Masao Takahashi , Hiroyuki Tsujikawa , Seijiro Kojima
- 申请人: Kenji Shimazaki , Kazuhiro Sato , Takahiro Ichinomiya , Shozo Hirano , Masao Takahashi , Hiroyuki Tsujikawa , Seijiro Kojima
- 申请人地址: JP Osaka
- 专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人地址: JP Osaka
- 代理机构: McDermott Will & Emery LLP
- 优先权: JP2004-001347 20040106
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
An impedance of a power supply wire is calculated based on design data of a semiconductor integrated circuit, a frequency characteristic of the calculated impedance is obtained, and a design of the semiconductor integrated circuit is changed based on the obtained frequency characteristic. As the above-described impedance, an impedance between power supplies that are different in potential such as a power supply and a ground may be calculated, or an impedance between power supplies that are substantially the same in potential such as a power supply and an N-well power supply may be calculated. By a design modification, a wiring method, the number of pads, separation of power supplies, a type of package, a characteristic of an inductance element, a substrate structure, a distance between wires, a decoupling capacitance, a length of a wire, and a characteristic of a resistance element, for example, are changed.
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