公开(公告)号：US20050114054A1

公开(公告)日：2005-05-26

申请号：US10988833

申请日：2004-11-16

申请人： Kenji Shimazaki ,  Kazuhiro Sato ,  Takahiro Ichinomiya ,  Shozo Hirano ,  Masao Takahashi ,  Hiroyuki Tsujikawa ,  Seijiro Kojima

发明人： Kenji Shimazaki ,  Kazuhiro Sato ,  Takahiro Ichinomiya ,  Shozo Hirano ,  Masao Takahashi ,  Hiroyuki Tsujikawa ,  Seijiro Kojima

IPC分类号： G06F17/50 ,  G01R29/26 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H03K17/16

CPC分类号： G01R29/26

摘要： Based on design data of a semiconductor integrated circuit, an impedance related to a power supply wire is calculated, and based on the calculated impedance, a frequency characteristic of power supply noise is analyzed. In calculation of an impedance, an impedance between power supplies which are different in potential, e.g., a main power supply and a ground, may be calculated. Alternatively, an impedance between power supplies which are substantially the same in potential, e.g., a main power supply and an N-well power supply, may be calculated. The calculated impedance includes a wire capacitance between power supply wires, a substrate resistance, an impedance of a package connected to the power supply wires, and so on. Thus, it is possible to provide a method for analyzing power supply noise of a semiconductor integrated circuit, which can be executed at an early stage of a design process with a small amount of calculation.

摘要翻译： 基于半导体集成电路的设计数据，计算与电源线相关的阻抗，并且基于所计算的阻抗来分析电源噪声的频率特性。 在计算阻抗时，可以计算电位不同的电源之间的阻抗，例如主电源和接地。 或者，可以计算电位基本相同的电源之间的阻抗，例如主电源和N阱电源。 所计算的阻抗包括电源线之间的线电容，衬底电阻，连接到电源线的封装的阻抗等。 因此，可以提供一种用于分析半导体集成电路的电源噪声的方法，其可以在少量计算的设计过程的早期阶段执行。

公开(公告)号：US07278124B2

公开(公告)日：2007-10-02

申请号：US11024470

申请日：2004-12-30

申请人： Kenji Shimazaki ,  Kazuhiro Sato ,  Takahiro Ichinomiya ,  Shozo Hirano ,  Masao Takahashi ,  Hiroyuki Tsujikawa ,  Seijiro Kojima

发明人： Kenji Shimazaki ,  Kazuhiro Sato ,  Takahiro Ichinomiya ,  Shozo Hirano ,  Masao Takahashi ,  Hiroyuki Tsujikawa ,  Seijiro Kojima

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5063

摘要： An impedance of a power supply wire is calculated based on design data of a semiconductor integrated circuit, a frequency characteristic of the calculated impedance is obtained, and a design of the semiconductor integrated circuit is changed based on the obtained frequency characteristic. As the above-described impedance, an impedance between power supplies that are different in potential such as a power supply and a ground may be calculated, or an impedance between power supplies that are substantially the same in potential such as a power supply and an N-well power supply may be calculated. By a design modification, a wiring method, the number of pads, separation of power supplies, a type of package, a characteristic of an inductance element, a substrate structure, a distance between wires, a decoupling capacitance, a length of a wire, and a characteristic of a resistance element, for example, are changed.

摘要翻译： 基于半导体集成电路的设计数据计算电源线的阻抗，获得所计算的阻抗的频率特性，并且基于获得的频率特性改变半导体集成电路的设计。 作为上述阻抗，可以计算诸如电源和地之间的电位不同的电源之间的阻抗，或者在诸如电源和N之间的电位基本上相同的电源之间的阻抗 - 可以计算电源。 通过设计修改，布线方法，焊盘的数量，电源的分离，封装的类型，电感元件的特性，基板结构，电线之间的距离，去耦电容，电线的长度， 并且例如电阻元件的特性被改变。

公开(公告)号：US20050149894A1

公开(公告)日：2005-07-07

申请号：US11024470

申请日：2004-12-30

申请人： Kenji Shimazaki ,  Kazuhiro Sato ,  Takahiro Ichinomiya ,  Shozo Hirano ,  Masao Takahashi ,  Hiroyuki Tsujikawa ,  Seijiro Kojima

发明人： Kenji Shimazaki ,  Kazuhiro Sato ,  Takahiro Ichinomiya ,  Shozo Hirano ,  Masao Takahashi ,  Hiroyuki Tsujikawa ,  Seijiro Kojima

IPC分类号： G06F17/50 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

CPC分类号： G06F17/5036 ,  G06F17/5063

摘要： An impedance of a power supply wire is calculated based on design data of a semiconductor integrated circuit, a frequency characteristic of the calculated impedance is obtained, and a design of the semiconductor integrated circuit is changed based on the obtained frequency characteristic. As the above-described impedance, an impedance between power supplies that are different in potential such as a power supply and a ground may be calculated, or an impedance between power supplies that are substantially the same in potential such as a power supply and an N-well power supply may be calculated. By a design modification, a wiring method, the number of pads, separation of power supplies, a type of package, a characteristic of an inductance element, a substrate structure, a distance between wires, a decoupling capacitance, a length of a wire, and a characteristic of a resistance element, for example, are changed.

摘要翻译： 基于半导体集成电路的设计数据计算电源线的阻抗，获得所计算的阻抗的频率特性，并且基于获得的频率特性改变半导体集成电路的设计。 作为上述阻抗，可以计算诸如电源和地之间的电位不同的电源之间的阻抗，或者在诸如电源和N之间的电位基本上相同的电源之间的阻抗 - 可以计算电源。 通过设计修改，布线方法，焊盘的数量，电源的分离，封装的类型，电感元件的特性，基板结构，电线之间的距离，去耦电容，电线的长度， 并且例如电阻元件的特性被改变。

公开(公告)号：US07225418B2

公开(公告)日：2007-05-29

申请号：US10863231

申请日：2004-06-09

申请人： Kenji Shimazaki ,  Kazuhiro Sato ,  Takahiro Ichinomiya ,  Nobufusa Iwanishi ,  Naoki Amekawa ,  Masaaki Hirata ,  Shouzou Hirano

发明人： Kenji Shimazaki ,  Kazuhiro Sato ,  Takahiro Ichinomiya ,  Nobufusa Iwanishi ,  Naoki Amekawa ,  Masaaki Hirata ,  Shouzou Hirano

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G01R31/318357 ,  G01R31/31928

摘要： There are contained the step of forming voltage waveform information by calculating a voltage waveform of each instance of a semiconductor integrated circuit at a power-supply terminal based on circuit information and analyzing the voltage waveform of each instance, the step of forming voltage abstraction information by abstracting the voltage waveform information, and the step of calculating a delay value of the instance based on the voltage abstraction information.

摘要翻译： 包含通过基于电路信息计算电源端子处的半导体集成电路的每个实例的电压波形并分析各实例的电压波形来形成电压波形信息的步骤，通过以下步骤形成电压抽象信息： 抽取电压波形信息，以及基于电压抽象信息计算实例的延迟值的步骤。

公开(公告)号：US07480875B2

公开(公告)日：2009-01-20

申请号：US11312370

申请日：2005-12-21

申请人： Kazuhiro Satoh ,  Kenji Shimazaki ,  Takahiro Ichinomiya ,  Shouzou Hirano

发明人： Kazuhiro Satoh ,  Kenji Shimazaki ,  Takahiro Ichinomiya ,  Shouzou Hirano

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： In optimizing a necessary capacitance of a semiconductor integrated circuit, the capacitance optimization can be achieved with higher precision by optimizing an IR drop (voltage drop) while considering dynamically a cell activation rate. In other words, in estimating a power-supply capacitance inserted to suppress a voltage fluctuation of the power supply, an areal demerit can be reduced by reducing a necessary capacitance component as a whole while considering a cell activation rate in the circuit or by selecting the capacitance required to supplement only temporal portions whose power-supply fluctuation is wide after the estimation of a cell operating timing. Also, the process can be conducted in a short time at the early stage of design by using a wiring load model at the time of capacitance estimate.

摘要翻译： 在优化半导体集成电路的必要电容时，可以通过在动态地考虑电池激活率的同时优化IR降（电压降），以更高的精度实现电容优化。 换句话说，在估计插入的电源电容以抑制电源的电压波动时，通过在考虑电路中的单元激活率的同时通过减少所需的电容分量作为整体来减少面积，或者通过选择 仅在单元操作定时的估计之后补充电源波动较大的时间部分所需的电容。 此外，可以在设计的早期的短时间内通过在电容估计时使用布线负载模型来进行该过程。

公开(公告)号：US20060143585A1

公开(公告)日：2006-06-29

申请号：US11312370

申请日：2005-12-21

申请人： Kazuhiro Satoh ,  Kenji Shimazaki ,  Takahiro Ichinomiya ,  Shouzou Hirano

发明人： Kazuhiro Satoh ,  Kenji Shimazaki ,  Takahiro Ichinomiya ,  Shouzou Hirano

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： In optimizing a necessary capacitance of a semiconductor integrated circuit, the capacitance optimization can be achieved with higher precision by optimizing an IR drop (voltage drop) while considering dynamically a cell activation rate. In other words, in estimating a power-supply capacitance inserted to suppress a voltage fluctuation of the power supply, an areal demerit can be reduced by reducing a necessary capacitance component as a whole while considering a cell activation rate in the circuit or by selecting the capacitance required to supplement only temporal portions whose power-supply fluctuation is wide after the estimation of a cell operating timing. Also, the process can be conducted in a short time at the early stage of design by using a wiring load model at the time of capacitance estimate.

公开(公告)号：US20100100219A1

公开(公告)日：2010-04-22

申请号：US12523834

申请日：2008-11-14

申请人： Takahiro Ichinomiya ,  Takashi Hashimoto

发明人： Takahiro Ichinomiya ,  Takashi Hashimoto

IPC分类号： G06F17/50

CPC分类号： H01L27/0203 ,  H01L27/118

摘要： A manufacturing system which can restrain the margin of a semiconductor integrated circuit.The integrated circuit 3000 including a fixed circuit unit 3003 and a reconfigurable circuit unit 3004 outputs, to a configuration determining server, an operation time which was calculated by a detecting unit 3001 and a calculating unit 3002. The configuration determining server 3007, by using the operation time obtained from the integrated circuit 3000, calculates performance data which indicates the characteristics of the fixed circuit unit 3003, selects, based on the performance data, a piece of configuration information indicating a circuit configuration that is optimum for the processing of the reconfigurable circuit unit 3004, and outputs the selected piece of configuration information.The integrated circuit 3000 builds a circuit in the reconfigurable circuit unit 3004 in accordance with the output piece of configuration information.

摘要翻译： 能够抑制半导体集成电路的余量的制造系统。 包括固定电路单元3003和可重构电路单元3004的集成电路3000将由检测单元3001和计算单元3002计算出的操作时间输出到配置确定服务器。配置确定服务器3007通过使用 从集成电路3000获得的运算时间，计算表示固定电路单元3003的特性的性能数据，根据性能数据选择表示对于可重构电路的处理最佳的电路配置的一条配置信息 单元3004，并输出所选择的配置信息。 集成电路3000根据输出的配置信息构建可重构电路单元3004中的电路。

公开(公告)号：US08143913B2

公开(公告)日：2012-03-27

申请号：US12375853

申请日：2008-04-16

申请人： Takahiro Ichinomiya

发明人： Takahiro Ichinomiya

IPC分类号： H03K19/173

CPC分类号： H03K19/1774 ,  G06F1/10 ,  H03K5/1502 ,  H03K19/17784

摘要： A semiconductor integrated circuit judges whether a power unit is performing a discharge operation or a charge operation. To reduce clock skew between a plurality of logic blocks in the semiconductor integrated circuit, when the power unit is performing the charge operation, the semiconductor integrated circuit determines a logic block that needs to be operated for the execution of a target process, as an operation block whose operation is to be started, and, determines, in the rest of the logic blocks, a logic block having a termination rate whose value is larger than a value of the minimum termination rate, as the operation block whose operation is to be started, the value of the termination rate being larger by more than a predetermined value.

摘要翻译： 半导体集成电路判断电力单元是进行放电动作还是充电动作。 为了减少半导体集成电路中的多个逻辑块之间的时钟偏移，当功率单元正在进行充电操作时，半导体集成电路确定需要操作的逻辑块，以执行目标处理，作为操作 块，其操作开始，并且在剩余的逻辑块中确定具有值大于最小终止速率值的终止速率的逻辑块作为其操作要开始的操作块 ，终止率的值大于预定值。

公开(公告)号：US07579864B2

公开(公告)日：2009-08-25

申请号：US12093263

申请日：2006-11-15

申请人： Takahiro Ichinomiya

发明人： Takahiro Ichinomiya

IPC分类号： H03K19/173

CPC分类号： H03K19/1774 ,  H03K19/17784

摘要： The number of blocks that can be stopped when performing target processing in a programmable logic unit is obtained, and a stop rate of each of a plurality of logic blocks included in the programmable logic unit is calculated. The same number of logic blocks as the blocks that can be stopped are selected from among the plurality of logic blocks in ascending order of a stop rate, the selected logic blocks are determined as logic blocks whose operations are to be stopped, and the operations are stopped. As a technique of stopping an operation of a logic block, a gated clock technique, a power-off technique, or the like is used.

摘要翻译： 获得在可编程逻辑单元中执行目标处理时可以停止的块的数量，并且计算包括在可编程逻辑单元中的多个逻辑块中的每一个的停止率。 以停止率的升序从多个逻辑块中选择与可停止的块相同数量的逻辑块，所选择的逻辑块被确定为其操作将被停止的逻辑块，并且操作是 停了 作为停止逻辑块的动作的技术，使用门控时钟技术，断电技术等。

公开(公告)号：US20050256921A1

公开(公告)日：2005-11-17

申请号：US10891496

申请日：2004-07-15

申请人： Naoki Amekawa ,  Takahiro Ichinomiya ,  Kazuhiro Satoh

发明人： Naoki Amekawa ,  Takahiro Ichinomiya ,  Kazuhiro Satoh

IPC分类号： G06F17/50 ,  G06G7/00 ,  H01L21/82 ,  H01L27/04 ,  H03K5/14

CPC分类号： G06F17/5036

摘要： A delay calculation method considering a net adjacent to a delay calculation object net of a semiconductor integrated circuit includes: an adjacent net internal resistance selecting step of selecting a combination of static state of an adjacent net driving cell; a coupling capacitance grounding step of multiplying a coupling capacitance by a coefficient obtained from an internal resistance of the adjacent net driving cell selected by the adjacent net internal resistance selecting step, and the like, and grounding the value obtained thereby as the coupling capacitance of the delay calculating object net; and a delay value deriving step of deriving the delay value from a circuit obtained by these steps. A problem of the delay calculation method that an accurate delay value cannot be obtained because in actuality, the adjacent wire whose potential fluctuates is approximated to zero potential is solved by this structure.

摘要翻译： 考虑与半导体集成电路的延迟计算对象网相邻的网络的延迟计算方法包括：相邻的网络内部电阻选择步骤，选择相邻网络驱动单元的静态的组合; 耦合电容接地步骤，将耦合电容乘以由相邻的净内部电阻选择步骤选择的相邻净驱动单元的内部电阻获得的系数等，并将由此获得的值接地作为 延迟计算物体网; 以及延迟值导出步骤，从通过这些步骤获得的电路导出延迟值。 通过这种结构解决了实际上电位波动近似为零电位的相邻导线的滞后计算方法不能获得精确延迟值的问题。