公开(公告)号：US20050114054A1

公开(公告)日：2005-05-26

申请号：US10988833

申请日：2004-11-16

申请人： Kenji Shimazaki ,  Kazuhiro Sato ,  Takahiro Ichinomiya ,  Shozo Hirano ,  Masao Takahashi ,  Hiroyuki Tsujikawa ,  Seijiro Kojima

发明人： Kenji Shimazaki ,  Kazuhiro Sato ,  Takahiro Ichinomiya ,  Shozo Hirano ,  Masao Takahashi ,  Hiroyuki Tsujikawa ,  Seijiro Kojima

IPC分类号： G06F17/50 ,  G01R29/26 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H03K17/16

CPC分类号： G01R29/26

摘要： Based on design data of a semiconductor integrated circuit, an impedance related to a power supply wire is calculated, and based on the calculated impedance, a frequency characteristic of power supply noise is analyzed. In calculation of an impedance, an impedance between power supplies which are different in potential, e.g., a main power supply and a ground, may be calculated. Alternatively, an impedance between power supplies which are substantially the same in potential, e.g., a main power supply and an N-well power supply, may be calculated. The calculated impedance includes a wire capacitance between power supply wires, a substrate resistance, an impedance of a package connected to the power supply wires, and so on. Thus, it is possible to provide a method for analyzing power supply noise of a semiconductor integrated circuit, which can be executed at an early stage of a design process with a small amount of calculation.

摘要翻译： 基于半导体集成电路的设计数据，计算与电源线相关的阻抗，并且基于所计算的阻抗来分析电源噪声的频率特性。 在计算阻抗时，可以计算电位不同的电源之间的阻抗，例如主电源和接地。 或者，可以计算电位基本相同的电源之间的阻抗，例如主电源和N阱电源。 所计算的阻抗包括电源线之间的线电容，衬底电阻，连接到电源线的封装的阻抗等。 因此，可以提供一种用于分析半导体集成电路的电源噪声的方法，其可以在少量计算的设计过程的早期阶段执行。

公开(公告)号：US06434730B1

公开(公告)日：2002-08-13

申请号：US09484022

申请日：2000-01-18

申请人： Mitsumi Ito ,  Hiroyuki Tsujikawa ,  Seijiro Kojima ,  Masatoshi Sawada

发明人： Mitsumi Ito ,  Hiroyuki Tsujikawa ,  Seijiro Kojima ,  Masatoshi Sawada

IPC分类号： G06F1750

CPC分类号： H01L23/5223 ,  G06F17/5068 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： After a layout for a semiconductor device including power and ground lines has been defined, patterns for bypass capacitors, which will be located under the power lines, are created. In this case, a pattern for a semiconductor device, where a bypass capacitor array is inlaid and substrate contacts are located under ground lines, is defined based on design rules input. Next, power lines are extracted and resized. Thereafter, logical operations are performed to place the bypass capacitors and the bypass capacitors are resized. Subsequently, logical operations are performed to define interconnecting diffused layers and the diffused layers are resized. Since the patterns for the power lines have already been defined before the patterns for the bypass capacitors are created, the patterns for the bypass capacitors to be placed under the power lines can be defined automatically. Thus, a pattern for a miniaturized semiconductor device with reduced power supply noise can be created automatically.

摘要翻译： 在定义了包括电源和接地线的半导体器件的布局之后，创建将位于电力线下方的用于旁路电容器的图案。 在这种情况下，基于设计规则输入来定义用于嵌入旁路电容器阵列并且衬底接触的半导体器件的图案位于地线下方。 接下来，提取电源线并调整大小。 此后，进行逻辑运算以放置旁路电容器和旁路电容器大小。 随后，执行逻辑操作以定义互连扩散层，并且扩散层被调整大小。 由于在创建旁路电容器的图案之前已经定义了电源线的图案，因此可以自动定义用于放置在电力线下方的旁路电容器的图案。 因此，可以自动地产生具有降低的电源噪声的小型化半导体器件的图案。

公开(公告)号：US20100242011A1

公开(公告)日：2010-09-23

申请号：US12594271

申请日：2009-02-17

申请人： Kiyohito Mukai ,  Masanori Ito ,  Yoshinaga Okamoto ,  Seijiro Kojima

发明人： Kiyohito Mukai ,  Masanori Ito ,  Yoshinaga Okamoto ,  Seijiro Kojima

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G03F1/36 ,  H01L27/0207

摘要： In a semiconductor integrated circuit mask layout verification method, a layout pattern division condition 108, according to which a plurality of specific layout patterns that need to have identical circuit characteristics are included, is input in a condition input step 109. In a data division step 103, input mask layout design data is divided into a plurality of layout pattern groups according to the layout pattern division condition. In a standard pattern selection step 105, a standard pattern serving as a standard in pattern matching is selected for each of the divided layout pattern groups. In a pattern matching step 106, for each of the layout pattern groups, layout patterns included in that layout pattern group are compared with the standard pattern.

摘要翻译： 在半导体集成电路掩模布局验证方法中，在条件输入步骤109中输入需要包含具有相同电路特性的多个特定布局图案的布局图案划分条件108.在数据分割步骤 如图103所示，输入掩模布局设计数据根据布局图案划分条件被划分为多个布局图案组。 在标准图案选择步骤105中，为每个划分的布局图案组选择用作图案匹配中的标准的标准图案。 在图案匹配步骤106中，对于每个布局图案组，将包括在该布局图案组中的布局图案与标准图案进行比较。

公开(公告)号：US20110088006A1

公开(公告)日：2011-04-14

申请号：US12970499

申请日：2010-12-16

申请人： Seijiro KOJIMA ,  Masaomi TOYAMA ,  Tsutomu YOSHIDOME ,  Masanori ITO

发明人： Seijiro KOJIMA ,  Masaomi TOYAMA ,  Tsutomu YOSHIDOME ,  Masanori ITO

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  H01L27/0207

摘要： A method for verifying a match between layout patterns of elements provided in a semiconductor integrated circuit, includes a verification condition setting step of setting a verification condition including information about paired elements whose layout patterns should match each other, a layout data input step of inputting layout data including pattern information and arrangement information of the paired elements, and a mismatched pattern parameter calculation layout verifying step of comparing the layout patterns of the paired elements based on the verification condition and the layout data to calculate a distance between the paired elements and at least one mismatched pattern.

摘要翻译： 一种用于验证在半导体集成电路中提供的元件的布局图案之间的匹配的匹配的方法，包括：验证条件设置步骤，设置包括布局图案应该彼此匹配的成对元件的信息的验证条件;输入布局的布局数据输入步骤 包括配对元件的图案信息和排列信息的数据，以及基于验证条件和布局数据比较配对元件的布局图案的不匹配的图案参数计算布局验证步骤，以计算配对元件之间的距离和至少 一个不匹配的模式。

公开(公告)号：US07278124B2

公开(公告)日：2007-10-02

申请号：US11024470

申请日：2004-12-30

申请人： Kenji Shimazaki ,  Kazuhiro Sato ,  Takahiro Ichinomiya ,  Shozo Hirano ,  Masao Takahashi ,  Hiroyuki Tsujikawa ,  Seijiro Kojima

发明人： Kenji Shimazaki ,  Kazuhiro Sato ,  Takahiro Ichinomiya ,  Shozo Hirano ,  Masao Takahashi ,  Hiroyuki Tsujikawa ,  Seijiro Kojima

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5063

摘要： An impedance of a power supply wire is calculated based on design data of a semiconductor integrated circuit, a frequency characteristic of the calculated impedance is obtained, and a design of the semiconductor integrated circuit is changed based on the obtained frequency characteristic. As the above-described impedance, an impedance between power supplies that are different in potential such as a power supply and a ground may be calculated, or an impedance between power supplies that are substantially the same in potential such as a power supply and an N-well power supply may be calculated. By a design modification, a wiring method, the number of pads, separation of power supplies, a type of package, a characteristic of an inductance element, a substrate structure, a distance between wires, a decoupling capacitance, a length of a wire, and a characteristic of a resistance element, for example, are changed.

摘要翻译： 基于半导体集成电路的设计数据计算电源线的阻抗，获得所计算的阻抗的频率特性，并且基于获得的频率特性改变半导体集成电路的设计。 作为上述阻抗，可以计算诸如电源和地之间的电位不同的电源之间的阻抗，或者在诸如电源和N之间的电位基本上相同的电源之间的阻抗 - 可以计算电源。 通过设计修改，布线方法，焊盘的数量，电源的分离，封装的类型，电感元件的特性，基板结构，电线之间的距离，去耦电容，电线的长度， 并且例如电阻元件的特性被改变。

公开(公告)号：US20050149894A1

公开(公告)日：2005-07-07

申请号：US11024470

申请日：2004-12-30

申请人： Kenji Shimazaki ,  Kazuhiro Sato ,  Takahiro Ichinomiya ,  Shozo Hirano ,  Masao Takahashi ,  Hiroyuki Tsujikawa ,  Seijiro Kojima

发明人： Kenji Shimazaki ,  Kazuhiro Sato ,  Takahiro Ichinomiya ,  Shozo Hirano ,  Masao Takahashi ,  Hiroyuki Tsujikawa ,  Seijiro Kojima

IPC分类号： G06F17/50 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

CPC分类号： G06F17/5036 ,  G06F17/5063

摘要： An impedance of a power supply wire is calculated based on design data of a semiconductor integrated circuit, a frequency characteristic of the calculated impedance is obtained, and a design of the semiconductor integrated circuit is changed based on the obtained frequency characteristic. As the above-described impedance, an impedance between power supplies that are different in potential such as a power supply and a ground may be calculated, or an impedance between power supplies that are substantially the same in potential such as a power supply and an N-well power supply may be calculated. By a design modification, a wiring method, the number of pads, separation of power supplies, a type of package, a characteristic of an inductance element, a substrate structure, a distance between wires, a decoupling capacitance, a length of a wire, and a characteristic of a resistance element, for example, are changed.

摘要翻译： 基于半导体集成电路的设计数据计算电源线的阻抗，获得所计算的阻抗的频率特性，并且基于获得的频率特性改变半导体集成电路的设计。 作为上述阻抗，可以计算诸如电源和地之间的电位不同的电源之间的阻抗，或者在诸如电源和N之间的电位基本上相同的电源之间的阻抗 - 可以计算电源。 通过设计修改，布线方法，焊盘的数量，电源的分离，封装的类型，电感元件的特性，基板结构，电线之间的距离，去耦电容，电线的长度， 并且例如电阻元件的特性被改变。