Invention Grant
- Patent Title: Tri-gate devices and methods of fabrication
- Patent Title (中): 三栅极器件和制造方法
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Application No.: US11123565Application Date: 2005-05-06
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Publication No.: US07427794B2Publication Date: 2008-09-23
- Inventor: Robert S. Chau , Brian S. Doyle , Jack Kavalieros , Douglas Barlage , Suman Datta , Scott A. Hareland
- Applicant: Robert S. Chau , Brian S. Doyle , Jack Kavalieros , Douglas Barlage , Suman Datta , Scott A. Hareland
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Rahul D. Engineer
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/94
Abstract:
The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.
Public/Granted literature
- US20050199950A1 Tri-gate devices and methods of fabrication Public/Granted day:2005-09-15
Information query
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