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发明授权
US07453148B2 Structure of dielectric layers in built-up layers of wafer level package 失效
晶圆级封装层叠电介质层结构

Structure of dielectric layers in built-up layers of wafer level package
摘要：
The present invention provides a structure of elastic dielectric layers with certain through holes adjacent to the angle of a RDL of WLP to absorb the stress. The elastic dielectric layer is made from silicone based materials with specific range of CTE, elongation rate and hardness, which can improve the mechanical reliability of the structure during temperature cycling test. The CTE difference between the RDL and the elastic dielectric material still may cause the elastic dielectric layer crack; to solve this problem, The present invention further provides a structure of dielectric layers with certain open through holes adjacent to the curve portion of a RDL of WLP which can reduce the stress accumulated at area of the dielectric layer adjacent to the RDL/dielectric layer interface to solve the crack problem of the dielectric layer.
摘要（中）：

本发明提供了具有与WLP的RDL的角度相邻的某些通孔以吸收应力的弹性介电层的结构。 弹性介电层由具有特定范围的CTE，伸长率和硬度的硅酮基材料制成，这可以在温度循环测试期间提高结构的机械可靠性。 RDL和弹性介电材料之间的CTE差异仍然可能导致弹性介电层裂纹; 为了解决这个问题，本发明还提供了具有与WLP的RDL的曲线部分相邻的某些开放通孔的电介质层的结构，其可以减少在与RDL /介电层界面相邻的介电层的面积处积累的应力 以解决电介质层的裂纹问题。

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