公开(公告)号：US20080136004A1

公开(公告)日：2008-06-12

申请号：US11608404

申请日：2006-12-08

申请人： Wen-Kun Yang ,  Chun-Hui Yu ,  Chao-Nan Chou ,  Chih-Wei Lin ,  Ching-Shun Huang

发明人： Wen-Kun Yang ,  Chun-Hui Yu ,  Chao-Nan Chou ,  Chih-Wei Lin ,  Ching-Shun Huang

IPC分类号： H01L23/488 ,  H01L21/56

CPC分类号： H01L24/97 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/73209 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06586 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/81 ,  H01L2924/00012

摘要： To pick and place standard first chip size package on a base with a second chip for obtaining an appropriate stacking chip size package than the original chip size package. The package structure has a larger chip size package than the size of the traditional stacking package. Moreover, the terminal pins of the flip chip package may be located on peripheral of LGA package or on array of BGA package.

摘要翻译： 在第二个芯片的基座上选择和放置标准的第一个芯片尺寸封装，以获得比原始芯片尺寸封装更适合的堆叠芯片尺寸封装。 封装结构具有比传统堆叠封装尺寸更大的芯片尺寸封装。 此外，倒装芯片封装的端子引脚可以位于LGA封装的外围或BGA封装的阵列上。

公开(公告)号：US20080150130A1

公开(公告)日：2008-06-26

申请号：US11613247

申请日：2006-12-20

申请人： Wen-Kun Yang ,  Chun-Hui Yu ,  Chao-Nan Chou ,  Chih-Wei Lin ,  Ching-Shun Huang

发明人： Wen-Kun Yang ,  Chun-Hui Yu ,  Chao-Nan Chou ,  Chih-Wei Lin ,  Ching-Shun Huang

IPC分类号： H01L23/48

CPC分类号： H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/73267 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00

摘要： The present invention provides a structure of elastic dielectric layers with certain through holes adjacent to the angle of a RDL of WLP to absorb the stress. The elastic dielectric layer is made from silicone based materials with specific range of CTE, elongation rate and hardness, which can improve the mechanical reliability of the structure during temperature cycling test. The CTE difference between the RDL and the elastic dielectric material still may cause the elastic dielectric layer crack; to solve this problem, The present invention further provides a structure of dielectric layers with certain open through holes adjacent to the curve portion of a RDL of WLP which can reduce the stress accumulated at area of the dielectric layer adjacent to the RDL/dielectric layer interface to solve the crack problem of the dielectric layer.

摘要翻译： 本发明提供了具有与WLP的RDL的角度相邻的某些通孔以吸收应力的弹性介电层的结构。 弹性介电层由具有特定范围的CTE，伸长率和硬度的硅酮基材料制成，这可以在温度循环测试期间提高结构的机械可靠性。 RDL和弹性介电材料之间的CTE差异仍然可能导致弹性介电层裂纹; 为了解决这个问题，本发明还提供了具有与WLP的RDL的曲线部分相邻的某些开放通孔的电介质层的结构，其可以减少在与RDL /介电层界面相邻的介电层的面积处积累的应力 以解决电介质层的裂纹问题。

公开(公告)号：US07453148B2

公开(公告)日：2008-11-18

申请号：US11613247

申请日：2006-12-20

申请人： Wen-Kun Yang ,  Chun-Hui Yu ,  Chao-Nan Chou ,  Chih-Wei Lin ,  Ching-Shun Huang

发明人： Wen-Kun Yang ,  Chun-Hui Yu ,  Chao-Nan Chou ,  Chih-Wei Lin ,  Ching-Shun Huang

IPC分类号： H01L23/48

CPC分类号： H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/73267 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00

摘要： The present invention provides a structure of elastic dielectric layers with certain through holes adjacent to the angle of a RDL of WLP to absorb the stress. The elastic dielectric layer is made from silicone based materials with specific range of CTE, elongation rate and hardness, which can improve the mechanical reliability of the structure during temperature cycling test. The CTE difference between the RDL and the elastic dielectric material still may cause the elastic dielectric layer crack; to solve this problem, The present invention further provides a structure of dielectric layers with certain open through holes adjacent to the curve portion of a RDL of WLP which can reduce the stress accumulated at area of the dielectric layer adjacent to the RDL/dielectric layer interface to solve the crack problem of the dielectric layer.

摘要翻译： 本发明提供了具有与WLP的RDL的角度相邻的某些通孔以吸收应力的弹性介电层的结构。 弹性介电层由具有特定范围的CTE，伸长率和硬度的硅酮基材料制成，这可以在温度循环测试期间提高结构的机械可靠性。 RDL和弹性介电材料之间的CTE差异仍然可能导致弹性介电层裂纹; 为了解决这个问题，本发明还提供了具有与WLP的RDL的曲线部分相邻的某些开放通孔的电介质层的结构，其可以减少在与RDL /介电层界面相邻的介电层的面积处积累的应力 以解决电介质层的裂纹问题。

公开(公告)号：US20080088004A1

公开(公告)日：2008-04-17

申请号：US11549985

申请日：2006-10-17

申请人： Wen-Kun Yang ,  Chao-Nan Chou ,  Ching-Shun Huang

发明人： Wen-Kun Yang ,  Chao-Nan Chou ,  Ching-Shun Huang

IPC分类号： H01L23/48

CPC分类号： H01L23/3114 ,  H01L23/525 ,  H01L23/562 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00

摘要： The present invention discloses a structure of wafer level packaging. To use the elastic materials with low k dielectric constant and larger elongation properties as dielectric layers materials used for build up layers of semiconductor device packaging, it can improve the reliability, especially in the board level temperature cycling test. In principle, the elastic dielectric layers can absorb the stress due to CTE (Coefficient of Thermal Expansion) mismatching issue.

摘要翻译： 本发明公开了一种晶片级封装的结构。 为了使用具有低k介电常数和较大伸长性能的弹性材料作为用于建立半导体器件封装层的介电层材料，可以提高可靠性，特别是在电路板级温度循环测试中。 原则上，弹性介电层可以吸收由于CTE（热膨胀系数）不匹配问题引起的应力。

公开(公告)号：US20080197469A1

公开(公告)日：2008-08-21

申请号：US11708475

申请日：2007-02-21

申请人： Wen-Kun Yang ,  Hsien-Wen Hsu ,  Ya-Tzu Wu ,  Ching-Shun Huang

发明人： Wen-Kun Yang ,  Hsien-Wen Hsu ,  Ya-Tzu Wu ,  Ching-Shun Huang

IPC分类号： H01L23/48 ,  H01L21/00

CPC分类号： H01L25/0657 ,  H01L23/13 ,  H01L24/19 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15153 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01055

摘要： The present invention provides a structure of multi-chips package and Method of the same comprising a substrate with a pre-formed die receiving cavity formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and an elastic dielectric layer filled into a gap between the die and the substrate to absorb thermal mechanical stress; therefore the thickness of the package is reduced and the CTE mismatch of the structure is reduced. The present invention also provides a structure for SIP with higher reliability and lower manufacturing cost. the process is simpler and it is easy to form the multi-chips package than the traditional one. Therefore, the present invention discloses a fan-out WLP with reduced thickness and good CTE matching performance.

摘要翻译： 本发明提供了一种多芯片封装的结构及其方法，其包括在衬底的上表面内形成有预成型的模具容纳空腔的衬底。 通过粘合将芯片设置在模具接收腔内，并且将弹性介电层填充到模具和基板之间的间隙中以吸收热机械应力; 因此，封装的厚度减小，结构的CTE失配减小。 本发明还提供了具有更高可靠性和更低制造成本的SIP的结构。 该过程更简单，并且比传统的更容易形成多芯片封装。 因此，本发明公开了一种具有减小厚度和良好CTE匹配性能的扇出WLP。