公开(公告)号：US20130040423A1

公开(公告)日：2013-02-14

申请号：US13206602

申请日：2011-08-10

Applicant: Chih-Hang Tung ,  Chun Hui Yu ,  Chen-Hua Yu ,  Da-Yuan Shih

Inventor： Chih-Hang Tung ,  Chun Hui Yu ,  Chen-Hua Yu ,  Da-Yuan Shih

IPC: H01L21/56 ,  H01L21/82

CPC classification number: H01L25/50 ,  H01L21/4882 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76879 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L24/19 ,  H01L24/24 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/02311 ,  H01L2224/02381 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/08146 ,  H01L2224/12105 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/03

Abstract: A method of multi-chip wafer level packaging comprises forming a reconfigured wafer using a plurality of photo-sensitive material layers. A plurality of semiconductor chips and wafers are embedded in the photo-sensitive material layers. Furthermore, a variety of through assembly vias are formed in the photo-sensitive material layers. Each semiconductor chip embedded in the photo-sensitive material layers is connected to input/output pads through connection paths formed by the through assembly vias.

Abstract translation: 多芯片晶片级封装的方法包括使用多个感光材料层形成重新配置的晶片。 多个半导体芯片和晶片被嵌入到感光材料层中。 此外，在感光材料层中形成各种贯穿组装通孔。 嵌入在感光材料层中的每个半导体芯片通过由通孔组装通孔形成的连接路径连接到输入/输出焊盘。

公开(公告)号：US08338945B2

公开(公告)日：2012-12-25

申请号：US12953130

申请日：2010-11-23

Applicant: Chen-Hua Yu ,  Chun Hui Yu ,  Jing-Cheng Lin

Inventor： Chen-Hua Yu ,  Chun Hui Yu ,  Jing-Cheng Lin

IPC: H01L23/48

CPC classification number: H01L25/0655 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3157 ,  H01L23/36 ,  H01L23/42 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/81805

Abstract: Apparatus and methods for providing a molded chip interposer structure and assembly. A molded chip structure having at least two integrated circuit dies disposed within a mold compound is provided having the die bond pads on the bottom surface; and solder bumps are formed in the openings of a dielectric layer on the bottom surface, the solder bumps forming connections to the bond pads. An interposer having a die side surface and a board side surface is provided having bump lands receiving the solder bumps of the molded chip structure on the die side of the interposer. An underfill layer is formed between the die side of the interposer and the bottom surface of the molded chip structure surrounding the solder bumps. Methods for forming the molded chip interposer structure are disclosed.

Abstract translation: 用于提供模制芯片插入件结构和组装的装置和方法。 提供具有设置在模具化合物内的至少两个集成电路管芯的模制芯片结构，其具有底表面上的管芯接合焊盘; 并且在底表面上的电介质层的开口中形成焊料凸块，焊料凸块形成与焊盘的连接。 具有裸片侧表面和电路板侧表面的插入件设置有凸起焊盘，其在插入件的裸片侧接收模制芯片结构的焊料凸块。 在插入件的裸片侧和围绕焊料凸块的模制芯片结构的底表面之间形成底部填充层。 公开了用于形成模制芯片内插器结构的方法。

公开(公告)号：US20120061059A1

公开(公告)日：2012-03-15

申请号：US13033840

申请日：2011-02-24

Applicant: Yi-Li HSIAO ,  Chen-Hua Yu ,  Da-Yuan Shih ,  Chih-Hang Tung ,  Chun Hui Yu

Inventor： Yi-Li HSIAO ,  Chen-Hua Yu ,  Da-Yuan Shih ,  Chih-Hang Tung ,  Chun Hui Yu

IPC: F28D15/00

CPC classification number: F28D15/02 ,  H01L23/34 ,  H01L23/473 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An apparatus for cooling a stacked die package comprises a first die provided above a substrate; a second die above the first die; a cooling fluid in fluid communication with the first die and the second die, the cooling fluid for absorbing thermal energy from the first and the second die; a housing containing the first and second dies, the housing sealing the first and second dies from an environment, wherein the housing further includes a first opening and a second opening, the first and second openings being vertically displaced from one another; a conduit having one end connected to the first opening and the other end connected to the second opening, the conduit allowing the cooling liquid to circulate from the first opening to the second opening; a first temperature sensor being arranged to provide an output that is dependent on a local temperature at the first opening; and a second temperature sensor being arranged to provide an output that is dependent on a local temperature at the second opening, wherein the outputs of the first and second temperature sensors relative to each other are indicative of a level of the cooling fluid.

Abstract translation: 一种用于冷却堆叠的管芯封装的设备，包括设置在衬底上的第一管芯; 第一个模具上方的第二个模具; 与第一模具和第二模具流体连通的冷却流体，用于从第一模具和第二模具吸收热能的冷却流体; 壳体，其包含第一和第二模具，所述壳体将环境中的第一和第二模具密封，其中所述壳体还包括第一开口和第二开口，所述第一和第二开口彼此垂直移位; 导管，其一端连接到第一开口，另一端连接到第二开口，导管允许冷却液从第一开口循环到第二开口; 第一温度传感器被布置成提供依赖于第一开口处的局部温度的输出; 并且第二温度传感器被布置成提供取决于第二开口处的局部温度的输出，其中第一和第二温度传感器相对于彼此的输出指示冷却流体的水平。

公开(公告)号：US20080142939A1

公开(公告)日：2008-06-19

申请号：US11609944

申请日：2006-12-13

Applicant: Wen-Kun Yang ,  Chun-Hui Yu ,  Chih-Wei Lin

Inventor： Wen-Kun Yang ,  Chun-Hui Yu ,  Chih-Wei Lin

IPC: H01L23/12 ,  H01L21/58

CPC classification number: H01L24/96 ,  H01L21/6835 ,  H01L24/27 ,  H01L24/29 ,  H01L2221/68318 ,  H01L2221/68368 ,  H01L2224/29014 ,  H01L2224/2919 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01094 ,  H01L2924/0665 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/00

Abstract: The present invention discloses a tool structure for chip redistribution and method of chip redistribution. The tool structure comprises a base substrate, a separable adhesion film formed on the base substrate, and the patterned glues placed on the separable adhesion film for fixating the dice covered by the core paste materials formed on a fixed substrate. The fixed substrate is bonding on the core paste materials and dice to form the panel wafer. The method comprises printing the pluralities of patterned glues placed on the separable adhesion film and the bonding pluralities of dice covered by the core paste materials, and then, the fixed substrate is bonding on the core paste materials and pluralities of dice. The method further comprises curing and separating the glues and the pluralities of dice with the fixed substrate, and then cleaning the residual glues on the panel wafer (pluralities of dice).

Abstract translation: 本发明公开了一种用于芯片再分配的工具结构和芯片再分配方法。 工具结构包括基底基底，形成在基底基底上的可分离粘合膜，以及放置在可分离粘合膜上的图案化胶，用于固定由形成在固定基底上的芯糊材料覆盖的骰子。 固定基板粘合在芯糊材料和芯片上以形成面板晶片。 该方法包括印刷放置在可分离粘合膜上的多个图案化胶和由芯糊材料覆盖的多个骰子的接合，然后固定的基底粘合在芯糊材料和多个骰子上。 该方法还包括用固定基板固化和分离胶水和多个骰子，然后清洁面板晶片上的残留胶（多个骰子）。

公开(公告)号：US20080029877A1

公开(公告)日：2008-02-07

申请号：US11869154

申请日：2007-10-09

Applicant: Wen-Kun Yang ,  Chun Hui Yu ,  Jui-Hsien Chang ,  Hsien-Wen Hsu

Inventor： Wen-Kun Yang ,  Chun Hui Yu ,  Jui-Hsien Chang ,  Hsien-Wen Hsu

IPC: H01L23/48

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/2402 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01094 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2224/82 ,  H01L2924/00

Abstract: The present invention provides a semiconductor device package singulation method. The method comprises printing a photo epoxy layer on the back surface of a substrate of a wafer for marking the scribe lines to be diced. Then etching is performed through the substrate along the marks in the photo epoxy layer. Dicing the panel into individual package with a typical art designing knife, the step not only avoids the roughness on the edge of each die, but also decrease the cost of singulation process.

Abstract translation: 本发明提供一种半导体器件封装分割方法。 该方法包括在晶片的基板的背面上印刷光环氧树脂层，以标记要切割的划线。 然后沿着光环氧树脂层中的标记通过基板进行蚀刻。 通过典型的美术设计刀将面板切割成单独的包装，该步骤不仅避免了每个模具边缘的粗糙度，而且降低了切割过程的成本。

公开(公告)号：US07279782B2

公开(公告)日：2007-10-09

申请号：US11029929

申请日：2005-01-05

Applicant: Wen-Kun Yang ,  Chin-Chen Yang ,  Wen-Bin Sun ,  Jui-Hsien Chang ,  Chun Hui Yu ,  His-Ying Yuan

Inventor： Wen-Kun Yang ,  Chin-Chen Yang ,  Wen-Bin Sun ,  Jui-Hsien Chang ,  Chun Hui Yu ,  His-Ying Yuan

IPC: H01L23/02

CPC classification number: H01L27/14618 ,  H01L27/14625 ,  H01L27/14627 ,  H01L2224/48227 ,  H01L2924/10253 ,  H01L2924/16235 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A structure of package comprises a die placed on printed circuit board. A glass substrate is adhered on an adhesive film pattern to form an air gap area between the glass substrate and the chip. Micro lens are disposed on the chip. A lens holder is fixed on printed circuit board. The glass substrate can prevent the micro lens from particle contamination.

Abstract translation: 封装结构包括放置在印刷电路板上的管芯。 将玻璃基板粘附在粘合膜图案上以在玻璃基板和芯片之间形成气隙区域。 微透镜设置在芯片上。 透镜架固定在印刷电路板上。 玻璃基板可防止微透镜受到颗粒污染。

公开(公告)号：US20060145364A1

公开(公告)日：2006-07-06

申请号：US11026488

申请日：2004-12-30

Applicant: Wen-Kun Yang ,  Chin-Chen Yang ,  Cheng-hsien Chiu ,  Wen-Bin Sun ,  Kuang-Chi Chao ,  His-Ying Yuan ,  Chun-Hui Yu

Inventor： Wen-Kun Yang ,  Chin-Chen Yang ,  Cheng-hsien Chiu ,  Wen-Bin Sun ,  Kuang-Chi Chao ,  His-Ying Yuan ,  Chun-Hui Yu

IPC: H01L23/29

CPC classification number: H01L21/6835 ,  H01L23/5389 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/8385 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01094 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

Abstract: A filling paste structure and process of wafer level package is disclosed. The process comprises filling an adhesive material to fill among plurality of dice and cover the plurality of dice. The pluralities of dice are adhered to glue pattern with viscosity in common state formed on a removable substrate. A rigid substrate is coated by adhesive material to adhere the dice. Then, pluralities of dice are departed from the glue pattern by a special environment after attaching the rigid base substrate.

Abstract translation: 公开了一种填充浆料结构和晶片级封装的工艺。 该方法包括填充粘合剂材料以填充多个骰子并覆盖多个骰子。 多个骰子粘附在形成在可移除基底上的共同状态下的粘度的胶图案上。 用粘合剂材料涂覆刚性基材以粘附骰子。 然后，在连接刚性基底之后，多个骰子由特殊的环境离开胶合图案。

公开(公告)号：US20130277829A1

公开(公告)日：2013-10-24

申请号：US13452636

申请日：2012-04-20

Applicant: Kuo-Chung Yee ,  Chun Hui Yu

Inventor： Kuo-Chung Yee ,  Chun Hui Yu

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/10 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/10 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/81 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00

Abstract: A method of fabricating a three dimensional integrated circuit comprises forming a redistribution layer on a first side of a packaging component, forming a holding chamber in the redistribution layer, attaching an integrated circuit die on the first side of the packaging component, wherein an interconnect bump of the integrated circuit die is inserted into the holding chamber, applying a reflow process to the integrated circuit die and the packaging component and forming an encapsulation layer on the packaging component.

Abstract translation: 一种制造三维集成电路的方法包括在包装部件的第一侧上形成再分配层，在再分布层中形成保持室，将集成电路管芯附接在包装部件的第一侧上，其中互连凸块 的集成电路管芯插入到保持室中，对集成电路管芯和封装部件进行回流处理，并在封装部件上形成封装层。

公开(公告)号：US07400037B2

公开(公告)日：2008-07-15

申请号：US11026488

申请日：2004-12-30

Applicant: Wen-Kun Yang ,  Chin-Chen Yang ,  Cheng-hsien Chiu ,  Wen-Bin Sun ,  Kuang-Chi Chao ,  His-Ying Yuan ,  Chun-Hui Yu

Inventor： Wen-Kun Yang ,  Chin-Chen Yang ,  Cheng-hsien Chiu ,  Wen-Bin Sun ,  Kuang-Chi Chao ,  His-Ying Yuan ,  Chun-Hui Yu

IPC: H01L23/34

CPC classification number: H01L21/6835 ,  H01L23/5389 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/8385 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01094 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

Abstract: A filling paste structure and process of wafer level package is disclosed. The process comprises filling an adhesive material to fill among plurality of dice and cover the plurality of dice. The pluralities of dice are adhered to glue pattern with viscosity in common state formed on a removable substrate. A rigid substrate is coated by adhesive material to adhere the dice. Then, pluralities of dice are departed from the glue pattern by a special environment after attaching the rigid base substrate.

Abstract translation: 公开了一种填充浆料结构和晶片级封装的工艺。 该方法包括填充粘合剂材料以填充多个骰子并覆盖多个骰子。 多个骰子粘附在形成在可移除基底上的共同状态下的粘度的胶图案上。 用粘合剂材料涂覆刚性基材以粘附骰子。 然后，在连接刚性基底之后，多个骰子由特殊的环境离开胶合图案。

公开(公告)号：US20080150130A1

公开(公告)日：2008-06-26

申请号：US11613247

申请日：2006-12-20

Applicant: Wen-Kun Yang ,  Chun-Hui Yu ,  Chao-Nan Chou ,  Chih-Wei Lin ,  Ching-Shun Huang

Inventor： Wen-Kun Yang ,  Chun-Hui Yu ,  Chao-Nan Chou ,  Chih-Wei Lin ,  Ching-Shun Huang

IPC: H01L23/48

CPC classification number: H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/73267 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00

Abstract: The present invention provides a structure of elastic dielectric layers with certain through holes adjacent to the angle of a RDL of WLP to absorb the stress. The elastic dielectric layer is made from silicone based materials with specific range of CTE, elongation rate and hardness, which can improve the mechanical reliability of the structure during temperature cycling test. The CTE difference between the RDL and the elastic dielectric material still may cause the elastic dielectric layer crack; to solve this problem, The present invention further provides a structure of dielectric layers with certain open through holes adjacent to the curve portion of a RDL of WLP which can reduce the stress accumulated at area of the dielectric layer adjacent to the RDL/dielectric layer interface to solve the crack problem of the dielectric layer.

Abstract translation: 本发明提供了具有与WLP的RDL的角度相邻的某些通孔以吸收应力的弹性介电层的结构。 弹性介电层由具有特定范围的CTE，伸长率和硬度的硅酮基材料制成，这可以在温度循环测试期间提高结构的机械可靠性。 RDL和弹性介电材料之间的CTE差异仍然可能导致弹性介电层裂纹; 为了解决这个问题，本发明还提供了具有与WLP的RDL的曲线部分相邻的某些开放通孔的电介质层的结构，其可以减少在与RDL /介电层界面相邻的介电层的面积处积累的应力 以解决电介质层的裂纹问题。